183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2c7964f86SEnric Balletbò i Serra /* 3c7964f86SEnric Balletbò i Serra * ti_omap3_common.h 4c7964f86SEnric Balletbò i Serra * 5c7964f86SEnric Balletbò i Serra * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 6c7964f86SEnric Balletbò i Serra * 7c7964f86SEnric Balletbò i Serra * For more details, please see the technical documents listed at 8c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3530 9c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/omap3630 10c7964f86SEnric Balletbò i Serra * http://www.ti.com/product/dm3730 11c7964f86SEnric Balletbò i Serra */ 12c7964f86SEnric Balletbò i Serra 13c7964f86SEnric Balletbò i Serra #ifndef __CONFIG_TI_OMAP3_COMMON_H__ 14c7964f86SEnric Balletbò i Serra #define __CONFIG_TI_OMAP3_COMMON_H__ 15c7964f86SEnric Balletbò i Serra 163709844fSAlbert ARIBAUD /* 173709844fSAlbert ARIBAUD * High Level Configuration Options 183709844fSAlbert ARIBAUD */ 193709844fSAlbert ARIBAUD 20c7964f86SEnric Balletbò i Serra #include <asm/arch/cpu.h> 21987ec585SNishanth Menon #include <asm/arch/omap.h> 22c7964f86SEnric Balletbò i Serra 23c7964f86SEnric Balletbò i Serra /* Clock Defines */ 24c7964f86SEnric Balletbò i Serra #define V_OSCK 26000000 /* Clock output from T2 */ 25c7964f86SEnric Balletbò i Serra #define V_SCLK (V_OSCK >> 1) 26c7964f86SEnric Balletbò i Serra 27c7964f86SEnric Balletbò i Serra /* NS16550 Configuration */ 28c7964f86SEnric Balletbò i Serra #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 29c7b9686dSThomas Chou #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 30313ed5d5SDerald D. Woods #if !defined(CONFIG_DM_SERIAL) 31*750df197SAdam Ford #define CONFIG_SYS_NS16550_SERIAL 32c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_REG_SIZE (-4) 33313ed5d5SDerald D. Woods #endif /* !CONFIG_DM_SERIAL */ 34c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 35c7964f86SEnric Balletbò i Serra 115200} 36c7964f86SEnric Balletbò i Serra 37c7964f86SEnric Balletbò i Serra /* Select serial console configuration */ 38b3f4ca11SSimon Glass #ifdef CONFIG_SPL_BUILD 39bdaf24f8SAdam Ford #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 40bdaf24f8SAdam Ford #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 41c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 42b3f4ca11SSimon Glass #endif 43c7964f86SEnric Balletbò i Serra 44c7964f86SEnric Balletbò i Serra /* Physical Memory Map */ 45c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 46c7964f86SEnric Balletbò i Serra #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 47c7964f86SEnric Balletbò i Serra 48c7964f86SEnric Balletbò i Serra /* 49c7964f86SEnric Balletbò i Serra * OMAP3 has 12 GP timers, they can be driven by the system clock 50c7964f86SEnric Balletbò i Serra * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 51c7964f86SEnric Balletbò i Serra * This rate is divided by a local divisor. 52c7964f86SEnric Balletbò i Serra */ 53c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 54c7964f86SEnric Balletbò i Serra 55c7964f86SEnric Balletbò i Serra #define CONFIG_SYS_MONITOR_LEN (256 << 10) 56c7964f86SEnric Balletbò i Serra 57c7964f86SEnric Balletbò i Serra /* SPL */ 58c7964f86SEnric Balletbò i Serra #define CONFIG_SPL_TEXT_BASE 0x40200800 59d3289aacSTom Rini #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ 60d3289aacSTom Rini (64 << 20)) 61d3289aacSTom Rini 62c7964f86SEnric Balletbò i Serra #ifdef CONFIG_NAND 63df4dbb5dSTom Rini #define CONFIG_SYS_NAND_BASE 0x30000000 64c7964f86SEnric Balletbò i Serra #endif 65c7964f86SEnric Balletbò i Serra 66c7964f86SEnric Balletbò i Serra /* Now bring in the rest of the common code. */ 679a0f4004SNishanth Menon #include <configs/ti_armv7_omap.h> 68c7964f86SEnric Balletbò i Serra 69c7964f86SEnric Balletbò i Serra #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ 70