Home
last modified time | relevance | path

Searched full:sdclk (Results 1 – 25 of 47) sorted by relevance

12

/openbmc/u-boot/drivers/mmc/
H A Dtmio-common.h55 #define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
56 #define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
57 #define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
58 #define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
59 #define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
60 #define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
61 #define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
62 #define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
63 #define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
64 #define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
[all …]
H A Dsdhci-cadence.c81 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
82 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
H A Ds5p_sdhci.c54 * Inverter delay means10ns delay if SDCLK 50MHz setting in s5p_sdhci_set_control_reg()
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dcdns,sdhci.yaml92 cdns,phy-dll-delay-sdclk:
94 Value of the delay introduced on the sdclk output for all modes except
100 cdns,phy-dll-delay-sdclk-hsmmc:
102 Value of the delay introduced on the sdclk output for HS200, HS400 and
155 cdns,phy-dll-delay-sdclk = <0>;
H A Dmarvell,xenon-sdhci.yaml230 clocks = <&sdclk 0>, <&axi_clk 0>;
272 clocks = <&sdclk 0>;
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-xenon-phy.c238 * 1. SDCLK frequency changes.
239 * 2. SDCLK is stopped and re-enabled.
490 * 2. SDCLK is higher than 52MHz in xenon_emmc_phy_strobe_delay_adj()
512 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
805 * PHY setting should be adjusted when SDCLK frequency, Bus Width
H A Dsdhci-of-aspeed.c261 * period of SDCLK = period of SDMCLK. in aspeed_sdhci_set_clock()
264 * period of SDCLK = period of SDMCLK * 2 * (EMMC12C[7:6], EMMC[15:8]) in aspeed_sdhci_set_clock()
544 dev_err(&pdev->dev, "Unable to enable SDCLK\n"); in aspeed_sdc_probe()
H A Dsdhci-cadence.c98 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
99 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
H A Dsdhci-xenon.c51 /* Set SDCLK-off-while-idle */
471 /* Disable SDCLK-Off-While-Idle before card init */ in xenon_sdhc_prepare()
/openbmc/u-boot/include/configs/
H A Dzipitz2.h83 #define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=System…
/openbmc/u-boot/drivers/ram/
H A Dstm32_sdram.c114 u8 sdclk; member
178 writel(control->sdclk << FMC_SDCR_SDCLK_SHIFT in stm32_sdram_init()
/openbmc/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
153 * run SDCLK at half speed. in sdram_calculate_timing()
/openbmc/u-boot/board/freescale/mx6memcal/
H A Dspl.c58 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
117 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
/openbmc/u-boot/board/bachmann/ot1200/
H A Dot1200_spl.c12 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */
/openbmc/u-boot/board/barco/platinum/
H A Dspl_picon.c27 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
H A Dspl_titanium.c27 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
/openbmc/u-boot/arch/arm/dts/
H A Dstm32f429-disco-u-boot.dtsi200 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK */
H A Duniphier-ld11.dtsi442 cdns,phy-dll-delay-sdclk = <21>;
443 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Dstm32f469-disco-u-boot.dtsi224 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
H A Dstm32429i-eval-u-boot.dtsi225 <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
H A Duniphier-pxs3.dtsi362 cdns,phy-dll-delay-sdclk = <21>;
363 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-ld20.dtsi571 cdns,phy-dll-delay-sdclk = <21>;
572 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
/openbmc/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi462 cdns,phy-dll-delay-sdclk = <21>;
463 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
H A Duniphier-ld20.dtsi598 cdns,phy-dll-delay-sdclk = <21>;
599 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
/openbmc/u-boot/board/gateworks/gw_ventana/
H A Dgw_ventana_spl.c29 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
89 /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */

12