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/openbmc/linux/include/soc/rockchip/
H A Drk3399_grf.h13 #define RK3399_PMUGRF_OS_REG2 0x308
/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hwio.h13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]
/openbmc/qemu/include/hw/timer/
H A Dnrf51_timer.h5 * + sysbus MMIO regions 0: GPIO registers
24 #define NRF51_TIMER_TASK_START 0x000
25 #define NRF51_TIMER_TASK_STOP 0x004
26 #define NRF51_TIMER_TASK_COUNT 0x008
27 #define NRF51_TIMER_TASK_CLEAR 0x00C
28 #define NRF51_TIMER_TASK_SHUTDOWN 0x010
29 #define NRF51_TIMER_TASK_CAPTURE_0 0x040
30 #define NRF51_TIMER_TASK_CAPTURE_3 0x04C
32 #define NRF51_TIMER_EVENT_COMPARE_0 0x140
33 #define NRF51_TIMER_EVENT_COMPARE_1 0x144
[all …]
/openbmc/linux/include/dt-bindings/reset/
H A Dhisi,hi6220-resets.h9 #define PERIPH_RSTDIS0_MMC0 0x000
10 #define PERIPH_RSTDIS0_MMC1 0x001
11 #define PERIPH_RSTDIS0_MMC2 0x002
12 #define PERIPH_RSTDIS0_NANDC 0x003
13 #define PERIPH_RSTDIS0_USBOTG_BUS 0x004
14 #define PERIPH_RSTDIS0_POR_PICOPHY 0x005
15 #define PERIPH_RSTDIS0_USBOTG 0x006
16 #define PERIPH_RSTDIS0_USBOTG_32K 0x007
17 #define PERIPH_RSTDIS1_HIFI 0x100
18 #define PERIPH_RSTDIS1_DIGACODEC 0x105
[all …]
/openbmc/qemu/include/hw/char/
H A Dnrf51_uart.h20 #define UART_SIZE 0x1000
25 REG32(UART_STARTRX, 0x000)
26 REG32(UART_STOPRX, 0x004)
27 REG32(UART_STARTTX, 0x008)
28 REG32(UART_STOPTX, 0x00C)
29 REG32(UART_SUSPEND, 0x01C)
31 REG32(UART_CTS, 0x100)
32 REG32(UART_NCTS, 0x104)
33 REG32(UART_RXDRDY, 0x108)
34 REG32(UART_TXDRDY, 0x11C)
[all …]
/openbmc/qemu/pc-bios/s390-ccw/
H A Diplb.h26 #define S390_IPL_TYPE_FCP 0x00
27 #define S390_IPL_TYPE_CCW 0x02
28 #define S390_IPL_TYPE_QEMU_SCSI 0xff
32 register unsigned long addr asm("0") = (unsigned long) iplb; in manage_iplb()
33 register unsigned long rc asm("1") = 0; in manage_iplb()
36 asm volatile ("diag %0,%2,0x308\n" in manage_iplb()
40 return rc == 0x01; in manage_iplb()
H A Djump2ipl.c14 #define KERN_IMAGE_START 0x010000UL
18 static uint64_t *reset_psw = 0, save_psw, ipl_continue;
55 * The IPL PSW is at address 0. We also must not overwrite the in jump_to_IPL_code()
75 "diag %%r1,%%r1,0x308\n\t" in jump_to_IPL_code()
97 * let's use 0 as an indication that we want to load the reset in jump_to_low_kernel()
98 * psw at 0x0 and not jump to the entry. in jump_to_low_kernel()
100 jump_to_IPL_code(0); in jump_to_low_kernel()
/openbmc/qemu/include/hw/misc/
H A Dnrf51_rng.h9 * + sysbus MMIO regions 0: Memory Region with tasks, events and registers
43 #define NRF51_RNG_SIZE 0x1000
45 #define NRF51_RNG_TASK_START 0x000
46 #define NRF51_RNG_TASK_STOP 0x004
47 #define NRF51_RNG_EVENT_VALRDY 0x100
48 #define NRF51_RNG_REG_SHORTS 0x200
49 #define NRF51_RNG_REG_SHORTS_VALRDY_STOP 0
50 #define NRF51_RNG_REG_INTEN 0x300
51 #define NRF51_RNG_REG_INTEN_VALRDY 0
52 #define NRF51_RNG_REG_INTENSET 0x304
[all …]
/openbmc/qemu/hw/misc/
H A Dallwinner-h3-ccu.c30 REG_PLL_CPUX = 0x0000, /* PLL CPUX Control */
31 REG_PLL_AUDIO = 0x0008, /* PLL Audio Control */
32 REG_PLL_VIDEO = 0x0010, /* PLL Video Control */
33 REG_PLL_VE = 0x0018, /* PLL VE Control */
34 REG_PLL_DDR = 0x0020, /* PLL DDR Control */
35 REG_PLL_PERIPH0 = 0x0028, /* PLL Peripherals 0 Control */
36 REG_PLL_GPU = 0x0038, /* PLL GPU Control */
37 REG_PLL_PERIPH1 = 0x0044, /* PLL Peripherals 1 Control */
38 REG_PLL_DE = 0x0048, /* PLL Display Engine Control */
39 REG_CPUX_AXI = 0x0050, /* CPUX/AXI Configuration */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-meson/
H A Dclock-axg.h18 #define HHI_GP0_PLL_CNTL 0x40
19 #define HHI_GP0_PLL_CNTL2 0x44
20 #define HHI_GP0_PLL_CNTL3 0x48
21 #define HHI_GP0_PLL_CNTL4 0x4c
22 #define HHI_GP0_PLL_CNTL5 0x50
23 #define HHI_GP0_PLL_STS 0x54
24 #define HHI_GP0_PLL_CNTL1 0x58
25 #define HHI_HIFI_PLL_CNTL 0x80
26 #define HHI_HIFI_PLL_CNTL2 0x84
27 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
/openbmc/linux/drivers/clk/meson/
H A Daxg.h19 #define HHI_GP0_PLL_CNTL 0x40
20 #define HHI_GP0_PLL_CNTL2 0x44
21 #define HHI_GP0_PLL_CNTL3 0x48
22 #define HHI_GP0_PLL_CNTL4 0x4c
23 #define HHI_GP0_PLL_CNTL5 0x50
24 #define HHI_GP0_PLL_STS 0x54
25 #define HHI_GP0_PLL_CNTL1 0x58
26 #define HHI_HIFI_PLL_CNTL 0x80
27 #define HHI_HIFI_PLL_CNTL2 0x84
28 #define HHI_HIFI_PLL_CNTL3 0x88
[all …]
H A Dg12a.h20 #define HHI_MIPI_CNTL0 0x000
21 #define HHI_MIPI_CNTL1 0x004
22 #define HHI_MIPI_CNTL2 0x008
23 #define HHI_MIPI_STS 0x00C
24 #define HHI_GP0_PLL_CNTL0 0x040
25 #define HHI_GP0_PLL_CNTL1 0x044
26 #define HHI_GP0_PLL_CNTL2 0x048
27 #define HHI_GP0_PLL_CNTL3 0x04C
28 #define HHI_GP0_PLL_CNTL4 0x050
29 #define HHI_GP0_PLL_CNTL5 0x054
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_gmac_cmn.h7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
[all …]
/openbmc/linux/sound/soc/tegra/
H A Dtegra186_asrc.h13 #define TEGRA186_ASRC_CFG 0x0
14 #define TEGRA186_ASRC_RATIO_INT_PART 0x4
15 #define TEGRA186_ASRC_RATIO_FRAC_PART 0x8
16 #define TEGRA186_ASRC_RATIO_LOCK_STATUS 0xc
17 #define TEGRA186_ASRC_MUTE_UNMUTE_DURATION 0x10
18 #define TEGRA186_ASRC_TX_THRESHOLD 0x14
19 #define TEGRA186_ASRC_RX_THRESHOLD 0x18
20 #define TEGRA186_ASRC_RATIO_COMP 0x1c
21 #define TEGRA186_ASRC_RX_STATUS 0x20
22 #define TEGRA186_ASRC_RX_CIF_CTRL 0x24
[all …]
/openbmc/linux/drivers/reset/starfive/
H A Dreset-starfive-jh7110.c24 .assert_offset = 0x2F8,
25 .status_offset = 0x308,
30 .assert_offset = 0x38,
31 .status_offset = 0x3C,
36 .assert_offset = 0x74,
37 .status_offset = 0x78,
42 .assert_offset = 0x38,
43 .status_offset = 0x3C,
48 .assert_offset = 0x48,
49 .status_offset = 0x4C,
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpsc_defs.h14 unsigned int pid; /* 0x000 */
15 unsigned char rsvd0[16]; /* 0x004 */
16 unsigned char rsvd1[4]; /* 0x014 */
17 unsigned int inteval; /* 0x018 */
18 unsigned char rsvd2[36]; /* 0x01C */
19 unsigned int merrpr0; /* 0x040 */
20 unsigned int merrpr1; /* 0x044 */
21 unsigned char rsvd3[8]; /* 0x048 */
22 unsigned int merrcr0; /* 0x050 */
23 unsigned int merrcr1; /* 0x054 */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimxrt1050-pinfunc.h10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
/openbmc/linux/arch/s390/kernel/
H A Drelocate_kernel.S25 * 0xf000 is a page_mask
30 basr %r13,0 # base address
34 lg %r5,0(%r2) # read another word for indirection page
36 tml %r5,0x1 # is it a destination page?
39 nill %r6,0xf000 # mask it out and...
42 tml %r5,0x2 # is it a indirection page?
44 nill %r5,0xf000 # YES, mask out,
48 tml %r5,0x4 # is it the done indicator?
52 tml %r5,0x8 # it should be a source indicator...
55 nill %r8,0xf000 # masking
[all …]
/openbmc/linux/sound/soc/qcom/qdsp6/
H A Dq6prm.h7 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_IBIT 0x100
9 #define Q6PRM_LPASS_CLK_ID_PRI_MI2S_EBIT 0x101
11 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_IBIT 0x102
13 #define Q6PRM_LPASS_CLK_ID_SEC_MI2S_EBIT 0x103
15 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_IBIT 0x104
17 #define Q6PRM_LPASS_CLK_ID_TER_MI2S_EBIT 0x105
19 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_IBIT 0x106
21 #define Q6PRM_LPASS_CLK_ID_QUAD_MI2S_EBIT 0x107
23 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_IBIT 0x108
25 #define Q6PRM_LPASS_CLK_ID_SPEAKER_I2S_EBIT 0x109
[all …]
/openbmc/linux/arch/parisc/include/asm/
H A Dropes.h47 #if DELAYED_RESOURCE_CNT > 0
56 #define SBA_SEARCH_SAMPLE 0x100
92 #define ASTRO_RUNWAY_PORT 0x582
93 #define IKE_MERCED_PORT 0x803
94 #define REO_MERCED_PORT 0x804
95 #define REOG_MERCED_PORT 0x805
96 #define PLUTO_MCKINLEY_PORT 0x880
114 #define SBA_PDIR_VALID_BIT 0x8000000000000000ULL
116 #define SBA_AGPGART_COOKIE (__force __le64) 0x0000badbadc0ffeeULL
118 #define SBA_FUNC_ID 0x0000 /* function id */
[all …]
/openbmc/linux/drivers/media/common/b2c2/
H A Dflexcop-reg.h11 FLEXCOP_UNK = 0,
18 FC_UNK = 0,
32 FC_USB = 0,
47 #define fc_data_Tag_ID_DVB 0x3e
48 #define fc_data_Tag_ID_ATSC 0x3f
49 #define fc_data_Tag_ID_IDSB 0x8b
51 #define fc_key_code_default 0x1
52 #define fc_key_code_even 0x2
53 #define fc_key_code_odd 0x3
64 FC_WRITE = 0,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml58 cpu 2, reg + 0x4;
59 cpu 3, reg + 0x8;
99 ranges = <0 0x802000 0x1000>;
100 reg = <0x802000 0x1000>;
102 smp-offset = <0x31c>;
103 resume-offset = <0x308>;
104 reboot-offset = <0x4>;
106 clock: clock@0 {
108 reg = <0 0x10000>;
116 reg = <0x10000000 0x1000>;
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dcache.json46 "EventCode": "0x49",
52 "EventCode": "0x59",
58 "EventCode": "0x200",
64 "EventCode": "0x202",
70 "EventCode": "0x208",
76 "EventCode": "0x209",
82 "EventCode": "0x300",
88 "EventCode": "0x302",
94 "EventCode": "0x308",
100 "EventCode": "0x309",
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dpci_nrtr_regs.h22 #define mmPCI_NRTR_HBW_MAX_CRED 0x100
24 #define mmPCI_NRTR_LBW_MAX_CRED 0x120
26 #define mmPCI_NRTR_DBG_E_ARB 0x300
28 #define mmPCI_NRTR_DBG_W_ARB 0x304
30 #define mmPCI_NRTR_DBG_N_ARB 0x308
32 #define mmPCI_NRTR_DBG_S_ARB 0x30C
34 #define mmPCI_NRTR_DBG_L_ARB 0x310
36 #define mmPCI_NRTR_DBG_E_ARB_MAX 0x320
38 #define mmPCI_NRTR_DBG_W_ARB_MAX 0x324
40 #define mmPCI_NRTR_DBG_N_ARB_MAX 0x328
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-stv0991/
H A Dstv0991_creg.h11 u32 version; /* offset 0x0 */
12 u32 hdpctl; /* offset 0x4 */
13 u32 hdpval; /* offset 0x8 */
14 u32 hdpgposet; /* offset 0xc */
15 u32 hdpgpoclr; /* offset 0x10 */
16 u32 hdpgpoval; /* offset 0x14 */
17 u32 stm_mux; /* offset 0x18 */
18 u32 sysctrl_1; /* offset 0x1c */
19 u32 sysctrl_2; /* offset 0x20 */
20 u32 sysctrl_3; /* offset 0x24 */
[all …]

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