197fb5e8dSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #ifndef _DPU_HWIO_H 625fdd593SJeykumar Sankaran #define _DPU_HWIO_H 725fdd593SJeykumar Sankaran 825fdd593SJeykumar Sankaran #include "dpu_hw_util.h" 925fdd593SJeykumar Sankaran 1025fdd593SJeykumar Sankaran /** 1125fdd593SJeykumar Sankaran * MDP TOP block Register and bit fields and defines 1225fdd593SJeykumar Sankaran */ 1325fdd593SJeykumar Sankaran #define DISP_INTF_SEL 0x004 1425fdd593SJeykumar Sankaran #define INTR_EN 0x010 1525fdd593SJeykumar Sankaran #define INTR_STATUS 0x014 1625fdd593SJeykumar Sankaran #define INTR_CLEAR 0x018 1725fdd593SJeykumar Sankaran #define INTR2_EN 0x008 1825fdd593SJeykumar Sankaran #define INTR2_STATUS 0x00c 19dbe2422bSDmitry Baryshkov #define SSPP_SPARE 0x028 2025fdd593SJeykumar Sankaran #define INTR2_CLEAR 0x02c 2125fdd593SJeykumar Sankaran #define HIST_INTR_EN 0x01c 2225fdd593SJeykumar Sankaran #define HIST_INTR_STATUS 0x020 2325fdd593SJeykumar Sankaran #define HIST_INTR_CLEAR 0x024 2425fdd593SJeykumar Sankaran #define SPLIT_DISPLAY_EN 0x2F4 2525fdd593SJeykumar Sankaran #define SPLIT_DISPLAY_UPPER_PIPE_CTRL 0x2F8 2625fdd593SJeykumar Sankaran #define DSPP_IGC_COLOR0_RAM_LUTN 0x300 2725fdd593SJeykumar Sankaran #define DSPP_IGC_COLOR1_RAM_LUTN 0x304 2825fdd593SJeykumar Sankaran #define DSPP_IGC_COLOR2_RAM_LUTN 0x308 29dbe2422bSDmitry Baryshkov #define DANGER_STATUS 0x360 30dbe2422bSDmitry Baryshkov #define SAFE_STATUS 0x364 3125fdd593SJeykumar Sankaran #define HW_EVENTS_CTL 0x37C 32dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_0_CTL 0x380 33dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_0_CTL2 0x384 34dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_0_LOAD_VALUE 0x388 35dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_1_CTL 0x390 36dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_1_CTL2 0x394 37dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_1_LOAD_VALUE 0x398 3825fdd593SJeykumar Sankaran #define CLK_CTRL3 0x3A8 3925fdd593SJeykumar Sankaran #define CLK_STATUS3 0x3AC 4025fdd593SJeykumar Sankaran #define CLK_CTRL4 0x3B0 4125fdd593SJeykumar Sankaran #define CLK_STATUS4 0x3B4 4225fdd593SJeykumar Sankaran #define CLK_CTRL5 0x3B8 4325fdd593SJeykumar Sankaran #define CLK_STATUS5 0x3BC 4425fdd593SJeykumar Sankaran #define CLK_CTRL7 0x3D0 4525fdd593SJeykumar Sankaran #define CLK_STATUS7 0x3D4 4625fdd593SJeykumar Sankaran #define SPLIT_DISPLAY_LOWER_PIPE_CTRL 0x3F0 4725fdd593SJeykumar Sankaran #define SPLIT_DISPLAY_TE_LINE_INTERVAL 0x3F4 4825fdd593SJeykumar Sankaran #define INTF_SW_RESET_MASK 0x3FC 4925fdd593SJeykumar Sankaran #define HDMI_DP_CORE_SELECT 0x408 5025fdd593SJeykumar Sankaran #define MDP_OUT_CTL_0 0x410 5125fdd593SJeykumar Sankaran #define MDP_VSYNC_SEL 0x414 52dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_2_CTL 0x420 53dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_2_CTL2 0x424 54dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_2_LOAD_VALUE 0x428 55dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_3_CTL 0x430 56dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_3_CTL2 0x434 57dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_3_LOAD_VALUE 0x438 58dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_4_CTL 0x440 59dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_4_CTL2 0x444 60dbe2422bSDmitry Baryshkov #define MDP_WD_TIMER_4_LOAD_VALUE 0x448 6125fdd593SJeykumar Sankaran #define DCE_SEL 0x450 6225fdd593SJeykumar Sankaran 63*43e3293fSDmitry Baryshkov #define MDP_PERIPH_TOP0 MDP_WD_TIMER_0_CTL 64*43e3293fSDmitry Baryshkov #define MDP_PERIPH_TOP0_END CLK_CTRL3 65*43e3293fSDmitry Baryshkov 6625fdd593SJeykumar Sankaran #endif /*_DPU_HWIO_H */ 67