hw/misc/allwinner-h3-ccu.c

30     REG_PLL_CPUX             = 0x0000, /* PLL CPUX Control */
31     REG_PLL_AUDIO            = 0x0008, /* PLL Audio Control */
32     REG_PLL_VIDEO            = 0x0010, /* PLL Video Control */
33     REG_PLL_VE               = 0x0018, /* PLL VE Control */
34     REG_PLL_DDR              = 0x0020, /* PLL DDR Control */
35     REG_PLL_PERIPH0          = 0x0028, /* PLL Peripherals 0 Control */
36     REG_PLL_GPU              = 0x0038, /* PLL GPU Control */
37     REG_PLL_PERIPH1          = 0x0044, /* PLL Peripherals 1 Control */
38     REG_PLL_DE               = 0x0048, /* PLL Display Engine Control */
39     REG_CPUX_AXI             = 0x0050, /* CPUX/AXI Configuration */
40     REG_APB1                 = 0x0054, /* ARM Peripheral Bus 1 Config */
41     REG_APB2                 = 0x0058, /* ARM Peripheral Bus 2 Config */
42     REG_DRAM_CFG             = 0x00F4, /* DRAM Configuration */
43     REG_MBUS                 = 0x00FC, /* MBUS Reset */
44     REG_PLL_TIME0            = 0x0200, /* PLL Stable Time 0 */
45     REG_PLL_TIME1            = 0x0204, /* PLL Stable Time 1 */
46     REG_PLL_CPUX_BIAS        = 0x0220, /* PLL CPUX Bias */
47     REG_PLL_AUDIO_BIAS       = 0x0224, /* PLL Audio Bias */
48     REG_PLL_VIDEO_BIAS       = 0x0228, /* PLL Video Bias */
49     REG_PLL_VE_BIAS          = 0x022C, /* PLL VE Bias */
50     REG_PLL_DDR_BIAS         = 0x0230, /* PLL DDR Bias */
51     REG_PLL_PERIPH0_BIAS     = 0x0234, /* PLL Peripherals 0 Bias */
52     REG_PLL_GPU_BIAS         = 0x023C, /* PLL GPU Bias */
53     REG_PLL_PERIPH1_BIAS     = 0x0244, /* PLL Peripherals 1 Bias */
54     REG_PLL_DE_BIAS          = 0x0248, /* PLL Display Engine Bias */
55     REG_PLL_CPUX_TUNING      = 0x0250, /* PLL CPUX Tuning */
56     REG_PLL_DDR_TUNING       = 0x0260, /* PLL DDR Tuning */
74     REG_PLL_CPUX_RST         = 0x00001000,
75     REG_PLL_AUDIO_RST        = 0x00035514,
76     REG_PLL_VIDEO_RST        = 0x03006207,
77     REG_PLL_VE_RST           = 0x03006207,
78     REG_PLL_DDR_RST          = 0x00001000,
79     REG_PLL_PERIPH0_RST      = 0x00041811,
80     REG_PLL_GPU_RST          = 0x03006207,
81     REG_PLL_PERIPH1_RST      = 0x00041811,
82     REG_PLL_DE_RST           = 0x03006207,
83     REG_CPUX_AXI_RST         = 0x00010000,
84     REG_APB1_RST             = 0x00001010,
85     REG_APB2_RST             = 0x01000000,
86     REG_DRAM_CFG_RST         = 0x00000000,
87     REG_MBUS_RST             = 0x80000000,
88     REG_PLL_TIME0_RST        = 0x000000FF,
89     REG_PLL_TIME1_RST        = 0x000000FF,
90     REG_PLL_CPUX_BIAS_RST    = 0x08100200,
91     REG_PLL_AUDIO_BIAS_RST   = 0x10100000,
92     REG_PLL_VIDEO_BIAS_RST   = 0x10100000,
93     REG_PLL_VE_BIAS_RST      = 0x10100000,
94     REG_PLL_DDR_BIAS_RST     = 0x81104000,
95     REG_PLL_PERIPH0_BIAS_RST = 0x10100010,
96     REG_PLL_GPU_BIAS_RST     = 0x10100000,
97     REG_PLL_PERIPH1_BIAS_RST = 0x10100010,
98     REG_PLL_DE_BIAS_RST      = 0x10100000,
99     REG_PLL_CPUX_TUNING_RST  = 0x0A101000,
100     REG_PLL_DDR_TUNING_RST   = 0x14880000,
110     case 0x308 ... AW_H3_CCU_IOSIZE:  in allwinner_h3_ccu_read()
111         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",  in allwinner_h3_ccu_read()
113         return 0;  in allwinner_h3_ccu_read()
134     case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */  in allwinner_h3_ccu_write()
142     case 0x308 ... AW_H3_CCU_IOSIZE:  in allwinner_h3_ccu_write()
143         qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",  in allwinner_h3_ccu_write()
147         qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",  in allwinner_h3_ccu_write()