/openbmc/qemu/target/arm/tcg/ |
H A D | translate-m-nocp.c | 135 tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); in trans_VSCCLRM() 137 tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK); in trans_VSCCLRM() 300 tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); in gen_branch_fpInactive() 335 tcg_gen_andi_i32(qc, tmp, FPCR_QC); in gen_M_fp_sysreg_write() 343 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); in gen_M_fp_sysreg_write() 345 tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); in gen_M_fp_sysreg_write() 393 tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); in gen_M_fp_sysreg_write() 460 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); in gen_M_fp_sysreg_read() 469 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); in gen_M_fp_sysreg_read() 479 tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); in gen_M_fp_sysreg_read() [all …]
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H A D | translate.c | 316 tcg_gen_andi_i32(var, var, ~3); in store_reg() 448 tcg_gen_andi_i32(tmp, tmp, 0x8000); in gen_add16() 449 tcg_gen_andi_i32(t0, t0, ~0x8000); in gen_add16() 450 tcg_gen_andi_i32(t1, t1, ~0x8000); in gen_add16() 556 tcg_gen_andi_i32(tmp1, t1, 0xff); in GEN_SHIFT() 758 tcg_gen_andi_i32(cpu_R[15], var, ~1); in gen_bx() 759 tcg_gen_andi_i32(var, var, 1); in gen_bx() 1481 tcg_gen_andi_i32(tmp, tmp, mask); in gen_iwmmxt_shift() 1813 tcg_gen_andi_i32(tmp, tmp, 7); in disas_iwmmxt_insn() 2666 tcg_gen_andi_i32(tmp, tmp, ~mask); in gen_set_psr() [all …]
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H A D | translate-vfp.c | 159 tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); in gen_update_fp_context() 403 tcg_gen_andi_i32(dest, dest, 0xffff); in trans_VSEL() 831 tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); in trans_VMSR_VMRS() 867 tcg_gen_andi_i32(tmp, tmp, 1 << 30); in trans_VMSR_VMRS() 906 tcg_gen_andi_i32(tmp, tmp, 0xffff); in trans_VMOV_half() 911 tcg_gen_andi_i32(tmp, tmp, 0xffff); in trans_VMOV_half()
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H A D | translate-neon.c | 2295 tcg_gen_andi_i32(var, var, 0xffff0000); in gen_neon_dup_high16() 3799 tcg_gen_andi_i32(rd, rd, 0xff00ff00); in gen_neon_trn_u8() 3800 tcg_gen_andi_i32(tmp, t1, 0x00ff00ff); in gen_neon_trn_u8() 3804 tcg_gen_andi_i32(t1, t1, 0x00ff00ff); in gen_neon_trn_u8() 3805 tcg_gen_andi_i32(tmp, t0, 0xff00ff00); in gen_neon_trn_u8() 3818 tcg_gen_andi_i32(tmp, t1, 0xffff); in gen_neon_trn_u16() 3821 tcg_gen_andi_i32(tmp, t0, 0xffff0000); in gen_neon_trn_u16()
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H A D | translate.h | 364 tcg_gen_andi_i32(p, p, ~bits); in clear_pstate_bits()
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H A D | translate-a64.c | 358 tcg_gen_andi_i32(tmp, tmp, 15); in check_lse2_align() 2063 tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); in gen_get_nzcv() 2084 tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); in gen_set_nzcv() 2086 tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); in gen_set_nzcv() 2089 tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); in gen_set_nzcv() 2092 tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); in gen_set_nzcv() 4868 tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); in disas_rotate_right_into_flags() 5881 tcg_gen_andi_i32(tcg_res, tcg_op, 0x7fff); in handle_fp_1src_half() 9245 tcg_gen_andi_i32(tcg_res, tcg_res, 0x7fff); in disas_simd_scalar_three_reg_same_fp16() 12541 tcg_gen_andi_i32(tcg_res, tcg_res, 0xffff); in disas_simd_two_reg_misc_fp16() [all …]
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H A D | translate-sve.c | 480 tcg_gen_andi_i32(cpu_ZF, t, 2); in do_pred_flags() 481 tcg_gen_andi_i32(cpu_CF, t, 1); in do_pred_flags() 2542 tcg_gen_andi_i32(last, last, vsz - 1); in incr_last_active() 2556 tcg_gen_andi_i32(last, last, vsz - 1); in wrap_last_active()
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/openbmc/qemu/target/m68k/ |
H A D | translate.c | 1610 tcg_gen_andi_i32(t0, t0, 0x22); in bcd_add() 1665 tcg_gen_andi_i32(t2, t2, 0x22); in bcd_sub() 3646 tcg_gen_andi_i32(X, lo, 1); in rotate32_x() 3761 tcg_gen_andi_i32(t0, src, 63); in DISAS_INSN() 3764 tcg_gen_andi_i32(t1, src, 31); in DISAS_INSN() 3792 tcg_gen_andi_i32(t0, src, 63); in DISAS_INSN() 3795 tcg_gen_andi_i32(t1, src, 7); in DISAS_INSN() 3824 tcg_gen_andi_i32(t0, src, 63); in DISAS_INSN() 4287 tcg_gen_andi_i32(addr, src, ~15); in m68k_copy_line() 4292 tcg_gen_andi_i32(addr, dst, ~15); in m68k_copy_line() [all …]
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/openbmc/qemu/target/sh4/ |
H A D | translate.c | 202 tcg_gen_andi_i32(cpu_sr, src, in gen_write_sr() 777 tcg_gen_andi_i32(t1, t1, 1); in _decode_opc() 877 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc() 899 tcg_gen_andi_i32(t0, REG(B7_4), 0x1f); in _decode_opc() 1131 tcg_gen_andi_i32(REG(0), REG(0), B7_0); in _decode_opc() 1140 tcg_gen_andi_i32(val, val, B7_0); in _decode_opc() 1270 tcg_gen_andi_i32(val, REG(0), B7_0); in _decode_opc() 1279 tcg_gen_andi_i32(val, val, B7_0); in _decode_opc() 1604 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc() 1607 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc() [all …]
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/openbmc/qemu/target/microblaze/ |
H A D | translate.c | 341 tcg_gen_andi_i32(out, ina, ~imm); in DO_TYPEA() 345 DO_TYPEBI(andi, false, tcg_gen_andi_i32) in DO_TYPEA() 352 tcg_gen_andi_i32(tmp, inb, 31); in DO_TYPEA() 359 tcg_gen_andi_i32(tmp, inb, 31); in gen_bsrl() 366 tcg_gen_andi_i32(tmp, inb, 31); in gen_bsll() 587 tcg_gen_andi_i32(cpu_msr_c, ina, 1); in DO_TYPEA() 596 tcg_gen_andi_i32(cpu_msr_c, ina, 1); in gen_src() 602 tcg_gen_andi_i32(cpu_msr_c, ina, 1); in gen_srl() 1202 tcg_gen_andi_i32(cpu_msr, cpu_msr, in trans_brki() 1549 tcg_gen_andi_i32(t_id, cpu_R[rb], 0xf); in do_get() [all …]
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/openbmc/qemu/scripts/coccinelle/ |
H A D | tcg_gen_extract.cocci | 55 tcg_gen_andi_i32@and_p 96 -tcg_gen_andi_i32@and_p(ret, ret, msk);
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/openbmc/qemu/target/loongarch/insn_trans/ |
H A D | trans_fmov.c.inc | 104 tcg_gen_andi_i32(temp, temp, mask); 105 tcg_gen_andi_i32(fcsr0, fcsr0, ~mask);
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/openbmc/qemu/target/rx/ |
H A D | translate.c | 1316 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); in trans_SHLL_rr() 1345 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in shiftr_imm() 1372 tcg_gen_andi_i32(count, cpu_regs[rs], 31); in shiftr_reg() 1375 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in shiftr_reg() 1437 tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); in trans_RORC() 1458 tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); in rx_rot() 1513 tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); in trans_REVW() 1516 tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); in trans_REVW() 1982 tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ 1993 tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ [all …]
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/openbmc/qemu/target/mips/tcg/ |
H A D | mxu_translate.c | 2203 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN() 2211 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN() 2234 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN() 2235 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); in gen_mxu_D16MAX_D16MIN() 2243 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN() 2244 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); in gen_mxu_D16MAX_D16MIN() 2297 tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN() 2333 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN() 2334 tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); in gen_mxu_Q8MAX_Q8MIN() 4202 tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); in gen_mxu_S32ALNI() [all …]
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H A D | translate.c | 1273 tcg_gen_andi_i32(t2, t2, 0xf); in gen_load_srsgpr() 1293 tcg_gen_andi_i32(t2, t2, 0xf); in gen_store_srsgpr() 8974 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1() 8980 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1() 8985 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1() 8990 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1() 9001 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1() 9011 tcg_gen_andi_i32(t0, t0, 1); in gen_compute_branch1() 9495 tcg_gen_andi_i32(fp0, fp0, 1); in gen_sel_s() 9499 tcg_gen_andi_i32(fp1, fp1, 1); in gen_sel_s() [all …]
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/openbmc/qemu/target/xtensa/ |
H A D | translate.c | 293 tcg_gen_andi_i32(cpu_SR[SAR], sa, 0x1f); in gen_right_shift_sar() 306 tcg_gen_andi_i32(dc->sar_m32, sa, 0x1f); in gen_left_shift_sar() 1411 tcg_gen_andi_i32(tmp, arg[1].in, 0x1f); in translate_bb() 1478 tcg_gen_andi_i32(tmp, arg[0].in, 1 << arg[0].imm); in translate_bp() 1602 tcg_gen_andi_i32(arg[0].out, tmp, maskimm); in translate_extui() 1880 tcg_gen_andi_i32(tmp, arg[2].in, 1 << arg[2].imm); in translate_movp() 2142 tcg_gen_andi_i32(arg[0].out, tmp, 0xfffffffc); in translate_rsr_ptevaddr() 2317 tcg_gen_andi_i32(s, s, 0x3f); in translate_sll() 2610 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, mask); in translate_wsr_ps() 2625 tcg_gen_andi_i32(cpu_SR[par[0]], arg[0].in, 0x3f); in translate_wsr_sar() [all …]
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/openbmc/qemu/tcg/ |
H A D | tcg-op-gvec.c | 1881 tcg_gen_andi_i32(t1, a, ~0xffff); in tcg_gen_vec_add16_i32() 2064 tcg_gen_andi_i32(t1, b, ~0xffff); in tcg_gen_vec_sub16_i32() 2814 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shl8i_i32() 2821 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shl16i_i32() 2879 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shr8i_i32() 2886 tcg_gen_andi_i32(d, d, mask); in tcg_gen_vec_shr16i_i32() 3358 tcg_gen_andi_i32(t, b, 31); in tcg_gen_shl_mod_i32() 3421 tcg_gen_andi_i32(t, b, 31); in tcg_gen_shr_mod_i32() 3484 tcg_gen_andi_i32(t, b, 31); in tcg_gen_sar_mod_i32() 3547 tcg_gen_andi_i32(t, b, 31); in tcg_gen_rotl_mod_i32() [all …]
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H A D | tcg-op.c | 388 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) in tcg_gen_andi_i32() function 911 tcg_gen_andi_i32(t1, arg2, mask); in tcg_gen_deposit_i32() 916 tcg_gen_andi_i32(ret, arg1, ~(mask << ofs)); in tcg_gen_deposit_i32() 933 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); in tcg_gen_deposit_z_i32() 974 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); in tcg_gen_deposit_z_i32() 993 tcg_gen_andi_i32(ret, arg, (1u << len) - 1); in tcg_gen_extract_i32() 1027 tcg_gen_andi_i32(ret, ret, (1u << len) - 1); in tcg_gen_extract_i32() 1290 tcg_gen_andi_i32(ret, arg, 0xffu); in tcg_gen_ext8u_i32() 1299 tcg_gen_andi_i32(ret, arg, 0xffffu); in tcg_gen_ext16u_i32() 1767 tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2); in tcg_gen_andi_i64() [all …]
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/openbmc/qemu/target/ppc/translate/ |
H A D | spe-impl.c.inc | 166 tcg_gen_andi_i32(t0, arg2, 0x3F); 182 tcg_gen_andi_i32(t0, arg2, 0x3F); 198 tcg_gen_andi_i32(t0, arg2, 0x3F); 210 tcg_gen_andi_i32(t0, arg2, 0x1F); 280 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \ 368 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3); 375 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
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H A D | fp-impl.c.inc | 537 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)],
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/openbmc/qemu/include/tcg/ |
H A D | tcg-op.h | 305 #define tcg_gen_andi_tl tcg_gen_andi_i32
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H A D | tcg-op-common.h | 86 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
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/openbmc/qemu/target/ppc/ |
H A D | translate.c | 1539 tcg_gen_andi_i32(src1, src1, 0xFF); in gen_cmprb() 2671 tcg_gen_andi_i32(t0, t0, mask); in gen_rlwinm() 2716 tcg_gen_andi_i32(t0, t0, 0x1f); in gen_rlwnm() 3477 tcg_gen_andi_i32(t1, t1, 0x7F); in gen_stswx() 4356 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); in gen_bcond() 4359 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); in gen_bcond() 4432 tcg_gen_andi_i32(t0, t0, bitmask); \ 4433 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ 4806 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); in gen_mtcrf() 4814 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); in gen_mtcrf()
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/openbmc/qemu/target/sparc/ |
H A D | translate.c | 2276 tcg_gen_andi_i32(r_tl, r_tl, MAXTL_MASK); in gen_load_trap_state_at_tl() 2585 tcg_gen_andi_i32(trap, trap, mask); in do_tcc() 2832 tcg_gen_andi_i32(tl, tl, MAXTL_MASK); in do_rdhtstate() 3413 tcg_gen_andi_i32(tl, tl, MAXTL_MASK); in TRANS()
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/openbmc/qemu/target/hppa/ |
H A D | translate.c | 2306 tcg_gen_andi_i32(level, level, 3); in trans_probe() 3429 tcg_gen_andi_i32(s32, s32, 31); in trans_shrp_sar() 3943 tcg_gen_andi_i32(dst, src, INT32_MAX); in gen_fabs_f()
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