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a01491a2 |
| 17-Nov-2023 |
Helge Deller <deller@gmx.de> |
target/hppa: Fix 64-bit SHRPD instruction
When shifting the two joined 64-bit registers right, shift the upper 64-bit register to the left and the lower 64-bit register to the right before merging t
target/hppa: Fix 64-bit SHRPD instruction
When shifting the two joined 64-bit registers right, shift the upper 64-bit register to the left and the lower 64-bit register to the right before merging them with OR.
Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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451d993d |
| 07-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX
Align the language with pa2.0, separating absolute and physical. The translation from absolute to physical depends on PSW.W, and we
target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDX
Align the language with pa2.0, separating absolute and physical. The translation from absolute to physical depends on PSW.W, and we prefer not to flush between changes, therefore use 2 mmu_idx.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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17fe594c |
| 07-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Introduce MMU_IDX_MMU_DISABLED
Reduce the number of direct checks against MMU_PHYS_IDX.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richar
target/hppa: Introduce MMU_IDX_MMU_DISABLED
Reduce the number of direct checks against MMU_PHYS_IDX.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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e5d487c9 |
| 07-Nov-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Use only low 2 immediate bits for PROBEI
During the conversion to decodetree, the 2-bit mask was lost.
Fixes: deee69a19fd ("target/hppa: Convert memory management insns") Reviewed-by:
target/hppa: Use only low 2 immediate bits for PROBEI
During the conversion to decodetree, the 2-bit mask was lost.
Fixes: deee69a19fd ("target/hppa: Convert memory management insns") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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881d1073 |
| 07-Nov-2023 |
Helge Deller <deller@gmx.de> |
target/hppa: Mask reserved PSW bits in expand_sm_imm
The system mask is a restricted subset of the psw, with only a couple of reserved bits. It is better to handle this up front in the translator t
target/hppa: Mask reserved PSW bits in expand_sm_imm
The system mask is a restricted subset of the psw, with only a couple of reserved bits. It is better to handle this up front in the translator than require helper_swap_system_mask to use cpu_hppa_get_psw and cpu_hppa_put_psw.
Signed-off-by: Helge Deller <deller@gmx.de> [rth: Handle this in expand_sm_imm not helper_swap_system_mask.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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f5b5c857 |
| 27-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Add unwind_breg to CPUHPPAState
Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed.
Signed-off-b
target/hppa: Add unwind_breg to CPUHPPAState
Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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4c34bab0 |
| 26-Oct-2023 |
Helge Deller <deller@gmx.de> |
target/hppa: Clear upper bits in mtctl for pa1.x
Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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eb25d10f |
| 26-Oct-2023 |
Helge Deller <deller@gmx.de> |
target/hppa: Add pa2.0 cpu local tlb flushes
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe".
PA
target/hppa: Add pa2.0 cpu local tlb flushes
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe".
PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b].
Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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b5caa17c |
| 26-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement pa2.0 data prefetch instructions
These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop.
Signed-off-by: Richard Henderson <r
target/hppa: Implement pa2.0 data prefetch instructions
These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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bc3da3cf |
| 18-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Return zero for r0 from load_gpr
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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a4db4a78 |
| 18-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Precompute zero into DisasContext
Reduce the number of times we look for the constant 0.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richa
target/hppa: Precompute zero into DisasContext
Reduce the number of times we look for the constant 0.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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4e7abdb1 |
| 21-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement PERMH
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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c2a7ee3f |
| 21-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement MIXH, MIXW
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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3bbb8e48 |
| 21-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement HSHLADD, HSHRADD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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151f309b |
| 21-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement HSHL, HSHR
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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1b3cb7c8 |
| 20-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement HAVG
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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10c9e58d |
| 20-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement HSUB
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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0843563f |
| 20-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement HADD
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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d265360f |
| 17-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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aac0f603 |
| 17-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Use tcg_temp_new_i64 not tcg_temp_new
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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967662cd |
| 17-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Remove remaining TARGET_REGISTER_BITS redirections
The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations.
Signed-off-by: Richard Henderso
target/hppa: Remove remaining TARGET_REGISTER_BITS redirections
The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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6fd0c7bc |
| 17-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Remove most of the TARGET_REGISTER_BITS redirections
Remove all but those intended to change type to or from i64.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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c53e401e |
| 17-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Remove TARGET_REGISTER_BITS
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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8577f354 |
| 12-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement IDTLBT, IITLBT
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit.
target/hppa: Implement IDTLBT, IITLBT
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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25460fc5 |
| 20-Sep-2023 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement STDBY
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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