1 #ifndef TARGET_ARM_TRANSLATE_H
2 #define TARGET_ARM_TRANSLATE_H
3
4 #include "cpu.h"
5 #include "tcg/tcg-op.h"
6 #include "tcg/tcg-op-gvec.h"
7 #include "exec/exec-all.h"
8 #include "exec/translator.h"
9 #include "exec/helper-gen.h"
10 #include "internals.h"
11 #include "cpu-features.h"
12
13 /* internal defines */
14
15 /*
16 * Save pc_save across a branch, so that we may restore the value from
17 * before the branch at the point the label is emitted.
18 */
19 typedef struct DisasLabel {
20 TCGLabel *label;
21 target_ulong pc_save;
22 } DisasLabel;
23
24 typedef struct DisasContext {
25 DisasContextBase base;
26 const ARMISARegisters *isar;
27
28 /* The address of the current instruction being translated. */
29 target_ulong pc_curr;
30 /*
31 * For CF_PCREL, the full value of cpu_pc is not known
32 * (although the page offset is known). For convenience, the
33 * translation loop uses the full virtual address that triggered
34 * the translation, from base.pc_start through pc_curr.
35 * For efficiency, we do not update cpu_pc for every instruction.
36 * Instead, pc_save has the value of pc_curr at the time of the
37 * last update to cpu_pc, which allows us to compute the addend
38 * needed to bring cpu_pc current: pc_curr - pc_save.
39 * If cpu_pc now contains the destination of an indirect branch,
40 * pc_save contains -1 to indicate that relative updates are no
41 * longer possible.
42 */
43 target_ulong pc_save;
44 target_ulong page_start;
45 uint32_t insn;
46 /* Nonzero if this instruction has been conditionally skipped. */
47 int condjmp;
48 /* The label that will be jumped to when the instruction is skipped. */
49 DisasLabel condlabel;
50 /* Thumb-2 conditional execution bits. */
51 int condexec_mask;
52 int condexec_cond;
53 /* M-profile ECI/ICI exception-continuable instruction state */
54 int eci;
55 /*
56 * trans_ functions for insns which are continuable should set this true
57 * after decode (ie after any UNDEF checks)
58 */
59 bool eci_handled;
60 int sctlr_b;
61 MemOp be_data;
62 #if !defined(CONFIG_USER_ONLY)
63 int user;
64 #endif
65 ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
66 uint8_t tbii; /* TBI1|TBI0 for insns */
67 uint8_t tbid; /* TBI1|TBI0 for data */
68 uint8_t tcma; /* TCMA1|TCMA0 for MTE */
69 bool ns; /* Use non-secure CPREG bank on access */
70 int fp_excp_el; /* FP exception EL or 0 if enabled */
71 int sve_excp_el; /* SVE exception EL or 0 if enabled */
72 int sme_excp_el; /* SME exception EL or 0 if enabled */
73 int vl; /* current vector length in bytes */
74 int svl; /* current streaming vector length in bytes */
75 bool vfp_enabled; /* FP enabled via FPSCR.EN */
76 int vec_len;
77 int vec_stride;
78 bool v7m_handler_mode;
79 bool v8m_secure; /* true if v8M and we're in Secure mode */
80 bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */
81 bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */
82 bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */
83 bool v7m_lspact; /* FPCCR.LSPACT set */
84 /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI
85 * so that top level loop can generate correct syndrome information.
86 */
87 uint32_t svc_imm;
88 int current_el;
89 GHashTable *cp_regs;
90 uint64_t features; /* CPU features bits */
91 bool aarch64;
92 bool thumb;
93 bool lse2;
94 /* Because unallocated encodings generate different exception syndrome
95 * information from traps due to FP being disabled, we can't do a single
96 * "is fp access disabled" check at a high level in the decode tree.
97 * To help in catching bugs where the access check was forgotten in some
98 * code path, we set this flag when the access check is done, and assert
99 * that it is set at the point where we actually touch the FP regs.
100 */
101 bool fp_access_checked;
102 bool sve_access_checked;
103 /* ARMv8 single-step state (this is distinct from the QEMU gdbstub
104 * single-step support).
105 */
106 bool ss_active;
107 bool pstate_ss;
108 /* True if the insn just emitted was a load-exclusive instruction
109 * (necessary for syndrome information for single step exceptions),
110 * ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
111 */
112 bool is_ldex;
113 /* True if AccType_UNPRIV should be used for LDTR et al */
114 bool unpriv;
115 /* True if v8.3-PAuth is active. */
116 bool pauth_active;
117 /* True if v8.5-MTE access to tags is enabled; index with is_unpriv. */
118 bool ata[2];
119 /* True if v8.5-MTE tag checks affect the PE; index with is_unpriv. */
120 bool mte_active[2];
121 /* True with v8.5-BTI and SCTLR_ELx.BT* set. */
122 bool bt;
123 /* True if any CP15 access is trapped by HSTR_EL2 */
124 bool hstr_active;
125 /* True if memory operations require alignment */
126 bool align_mem;
127 /* True if PSTATE.IL is set */
128 bool pstate_il;
129 /* True if PSTATE.SM is set. */
130 bool pstate_sm;
131 /* True if PSTATE.ZA is set. */
132 bool pstate_za;
133 /* True if non-streaming insns should raise an SME Streaming exception. */
134 bool sme_trap_nonstreaming;
135 /* True if the current instruction is non-streaming. */
136 bool is_nonstreaming;
137 /* True if MVE insns are definitely not predicated by VPR or LTPSIZE */
138 bool mve_no_pred;
139 /* True if fine-grained traps are active */
140 bool fgt_active;
141 /* True if fine-grained trap on ERET is enabled */
142 bool fgt_eret;
143 /* True if fine-grained trap on SVC is enabled */
144 bool fgt_svc;
145 /* True if FEAT_LSE2 SCTLR_ELx.nAA is set */
146 bool naa;
147 /*
148 * >= 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI.
149 * < 0, set by the current instruction.
150 */
151 int8_t btype;
152 /* A copy of cpu->dcz_blocksize. */
153 uint8_t dcz_blocksize;
154 /* A copy of cpu->gm_blocksize. */
155 uint8_t gm_blocksize;
156 /* True if this page is guarded. */
157 bool guarded_page;
158 /* Bottom two bits of XScale c15_cpar coprocessor access control reg */
159 int c15_cpar;
160 /* TCG op of the current insn_start. */
161 TCGOp *insn_start;
162 } DisasContext;
163
164 typedef struct DisasCompare {
165 TCGCond cond;
166 TCGv_i32 value;
167 } DisasCompare;
168
169 /* Share the TCG temporaries common between 32 and 64 bit modes. */
170 extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
171 extern TCGv_i64 cpu_exclusive_addr;
172 extern TCGv_i64 cpu_exclusive_val;
173
174 /*
175 * Constant expanders for the decoders.
176 */
177
negate(DisasContext * s,int x)178 static inline int negate(DisasContext *s, int x)
179 {
180 return -x;
181 }
182
plus_1(DisasContext * s,int x)183 static inline int plus_1(DisasContext *s, int x)
184 {
185 return x + 1;
186 }
187
plus_2(DisasContext * s,int x)188 static inline int plus_2(DisasContext *s, int x)
189 {
190 return x + 2;
191 }
192
plus_12(DisasContext * s,int x)193 static inline int plus_12(DisasContext *s, int x)
194 {
195 return x + 12;
196 }
197
times_2(DisasContext * s,int x)198 static inline int times_2(DisasContext *s, int x)
199 {
200 return x * 2;
201 }
202
times_4(DisasContext * s,int x)203 static inline int times_4(DisasContext *s, int x)
204 {
205 return x * 4;
206 }
207
times_8(DisasContext * s,int x)208 static inline int times_8(DisasContext *s, int x)
209 {
210 return x * 8;
211 }
212
times_2_plus_1(DisasContext * s,int x)213 static inline int times_2_plus_1(DisasContext *s, int x)
214 {
215 return x * 2 + 1;
216 }
217
rsub_64(DisasContext * s,int x)218 static inline int rsub_64(DisasContext *s, int x)
219 {
220 return 64 - x;
221 }
222
rsub_32(DisasContext * s,int x)223 static inline int rsub_32(DisasContext *s, int x)
224 {
225 return 32 - x;
226 }
227
rsub_16(DisasContext * s,int x)228 static inline int rsub_16(DisasContext *s, int x)
229 {
230 return 16 - x;
231 }
232
rsub_8(DisasContext * s,int x)233 static inline int rsub_8(DisasContext *s, int x)
234 {
235 return 8 - x;
236 }
237
shl_12(DisasContext * s,int x)238 static inline int shl_12(DisasContext *s, int x)
239 {
240 return x << 12;
241 }
242
neon_3same_fp_size(DisasContext * s,int x)243 static inline int neon_3same_fp_size(DisasContext *s, int x)
244 {
245 /* Convert 0==fp32, 1==fp16 into a MO_* value */
246 return MO_32 - x;
247 }
248
arm_dc_feature(DisasContext * dc,int feature)249 static inline int arm_dc_feature(DisasContext *dc, int feature)
250 {
251 return (dc->features & (1ULL << feature)) != 0;
252 }
253
get_mem_index(DisasContext * s)254 static inline int get_mem_index(DisasContext *s)
255 {
256 return arm_to_core_mmu_idx(s->mmu_idx);
257 }
258
disas_set_insn_syndrome(DisasContext * s,uint32_t syn)259 static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn)
260 {
261 /* We don't need to save all of the syndrome so we mask and shift
262 * out unneeded bits to help the sleb128 encoder do a better job.
263 */
264 syn &= ARM_INSN_START_WORD2_MASK;
265 syn >>= ARM_INSN_START_WORD2_SHIFT;
266
267 /* We check and clear insn_start_idx to catch multiple updates. */
268 assert(s->insn_start != NULL);
269 tcg_set_insn_start_param(s->insn_start, 2, syn);
270 s->insn_start = NULL;
271 }
272
curr_insn_len(DisasContext * s)273 static inline int curr_insn_len(DisasContext *s)
274 {
275 return s->base.pc_next - s->pc_curr;
276 }
277
278 /* is_jmp field values */
279 #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
280 /* CPU state was modified dynamically; exit to main loop for interrupts. */
281 #define DISAS_UPDATE_EXIT DISAS_TARGET_1
282 /* These instructions trap after executing, so the A32/T32 decoder must
283 * defer them until after the conditional execution state has been updated.
284 * WFI also needs special handling when single-stepping.
285 */
286 #define DISAS_WFI DISAS_TARGET_2
287 #define DISAS_SWI DISAS_TARGET_3
288 /* WFE */
289 #define DISAS_WFE DISAS_TARGET_4
290 #define DISAS_HVC DISAS_TARGET_5
291 #define DISAS_SMC DISAS_TARGET_6
292 #define DISAS_YIELD DISAS_TARGET_7
293 /* M profile branch which might be an exception return (and so needs
294 * custom end-of-TB code)
295 */
296 #define DISAS_BX_EXCRET DISAS_TARGET_8
297 /*
298 * For instructions which want an immediate exit to the main loop, as opposed
299 * to attempting to use lookup_and_goto_ptr. Unlike DISAS_UPDATE_EXIT, this
300 * doesn't write the PC on exiting the translation loop so you need to ensure
301 * something (gen_a64_update_pc or runtime helper) has done so before we reach
302 * return from cpu_tb_exec.
303 */
304 #define DISAS_EXIT DISAS_TARGET_9
305 /* CPU state was modified dynamically; no need to exit, but do not chain. */
306 #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10
307
308 #ifdef TARGET_AARCH64
309 void a64_translate_init(void);
310 void gen_a64_update_pc(DisasContext *s, target_long diff);
311 extern const TranslatorOps aarch64_translator_ops;
312 #else
a64_translate_init(void)313 static inline void a64_translate_init(void)
314 {
315 }
316
gen_a64_update_pc(DisasContext * s,target_long diff)317 static inline void gen_a64_update_pc(DisasContext *s, target_long diff)
318 {
319 }
320 #endif
321
322 void arm_test_cc(DisasCompare *cmp, int cc);
323 void arm_jump_cc(DisasCompare *cmp, TCGLabel *label);
324 void arm_gen_test_cc(int cc, TCGLabel *label);
325 MemOp pow2_align(unsigned i);
326 void unallocated_encoding(DisasContext *s);
327 void gen_exception_insn_el(DisasContext *s, target_long pc_diff, int excp,
328 uint32_t syn, uint32_t target_el);
329 void gen_exception_insn(DisasContext *s, target_long pc_diff,
330 int excp, uint32_t syn);
331
332 /* Return state of Alternate Half-precision flag, caller frees result */
get_ahp_flag(void)333 static inline TCGv_i32 get_ahp_flag(void)
334 {
335 TCGv_i32 ret = tcg_temp_new_i32();
336
337 tcg_gen_ld_i32(ret, tcg_env,
338 offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPSCR]));
339 tcg_gen_extract_i32(ret, ret, 26, 1);
340
341 return ret;
342 }
343
344 /* Set bits within PSTATE. */
set_pstate_bits(uint32_t bits)345 static inline void set_pstate_bits(uint32_t bits)
346 {
347 TCGv_i32 p = tcg_temp_new_i32();
348
349 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
350
351 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
352 tcg_gen_ori_i32(p, p, bits);
353 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
354 }
355
356 /* Clear bits within PSTATE. */
clear_pstate_bits(uint32_t bits)357 static inline void clear_pstate_bits(uint32_t bits)
358 {
359 TCGv_i32 p = tcg_temp_new_i32();
360
361 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
362
363 tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate));
364 tcg_gen_andi_i32(p, p, ~bits);
365 tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate));
366 }
367
368 /* If the singlestep state is Active-not-pending, advance to Active-pending. */
gen_ss_advance(DisasContext * s)369 static inline void gen_ss_advance(DisasContext *s)
370 {
371 if (s->ss_active) {
372 s->pstate_ss = 0;
373 clear_pstate_bits(PSTATE_SS);
374 }
375 }
376
377 /* Generate an architectural singlestep exception */
gen_swstep_exception(DisasContext * s,int isv,int ex)378 static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
379 {
380 /* Fill in the same_el field of the syndrome in the helper. */
381 uint32_t syn = syn_swstep(false, isv, ex);
382 gen_helper_exception_swstep(tcg_env, tcg_constant_i32(syn));
383 }
384
385 /*
386 * Given a VFP floating point constant encoded into an 8 bit immediate in an
387 * instruction, expand it to the actual constant value of the specified
388 * size, as per the VFPExpandImm() pseudocode in the Arm ARM.
389 */
390 uint64_t vfp_expand_imm(int size, uint8_t imm8);
391
392 /* Vector operations shared between ARM and AArch64. */
393 void gen_gvec_ceq0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
394 uint32_t opr_sz, uint32_t max_sz);
395 void gen_gvec_clt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
396 uint32_t opr_sz, uint32_t max_sz);
397 void gen_gvec_cgt0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
398 uint32_t opr_sz, uint32_t max_sz);
399 void gen_gvec_cle0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
400 uint32_t opr_sz, uint32_t max_sz);
401 void gen_gvec_cge0(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
402 uint32_t opr_sz, uint32_t max_sz);
403
404 void gen_gvec_mla(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
405 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
406 void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
407 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
408
409 void gen_gvec_cmtst(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
410 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
411 void gen_gvec_sshl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
412 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
413 void gen_gvec_ushl(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
414 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
415
416 void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
417 void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
418 void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b);
419 void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
420 void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
421
422 void gen_gvec_uqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
423 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
424 void gen_gvec_sqadd_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
425 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
426 void gen_gvec_uqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
427 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
428 void gen_gvec_sqsub_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
429 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
430
431 void gen_gvec_ssra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
432 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
433 void gen_gvec_usra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
434 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
435
436 void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
437 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
438 void gen_gvec_urshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
439 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
440 void gen_gvec_srsra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
441 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
442 void gen_gvec_ursra(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
443 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
444
445 void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
446 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
447 void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
448 int64_t shift, uint32_t opr_sz, uint32_t max_sz);
449
450 void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
451 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
452 void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
453 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
454
455 void gen_gvec_sabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
456 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
457 void gen_gvec_uabd(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
458 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
459
460 void gen_gvec_saba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
461 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
462 void gen_gvec_uaba(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
463 uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
464
465 /*
466 * Forward to the isar_feature_* tests given a DisasContext pointer.
467 */
468 #define dc_isar_feature(name, ctx) \
469 ({ DisasContext *ctx_ = (ctx); isar_feature_##name(ctx_->isar); })
470
471 /* Note that the gvec expanders operate on offsets + sizes. */
472 typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
473 typedef void GVecGen2iFn(unsigned, uint32_t, uint32_t, int64_t,
474 uint32_t, uint32_t);
475 typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
476 uint32_t, uint32_t, uint32_t);
477 typedef void GVecGen4Fn(unsigned, uint32_t, uint32_t, uint32_t,
478 uint32_t, uint32_t, uint32_t);
479
480 /* Function prototype for gen_ functions for calling Neon helpers */
481 typedef void NeonGenOneOpFn(TCGv_i32, TCGv_i32);
482 typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32);
483 typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32);
484 typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
485 typedef void NeonGenThreeOpEnvFn(TCGv_i32, TCGv_env, TCGv_i32,
486 TCGv_i32, TCGv_i32);
487 typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64);
488 typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64);
489 typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64);
490 typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64);
491 typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32);
492 typedef void NeonGenTwoOpWidenFn(TCGv_i64, TCGv_i32, TCGv_i32);
493 typedef void NeonGenOneSingleOpFn(TCGv_i32, TCGv_i32, TCGv_ptr);
494 typedef void NeonGenTwoSingleOpFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
495 typedef void NeonGenTwoDoubleOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr);
496 typedef void NeonGenOne64OpFn(TCGv_i64, TCGv_i64);
497 typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr);
498 typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32);
499 typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr);
500 typedef void AtomicThreeOpFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGArg, MemOp);
501 typedef void WideShiftImmFn(TCGv_i64, TCGv_i64, int64_t shift);
502 typedef void WideShiftFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i32);
503 typedef void ShiftImmFn(TCGv_i32, TCGv_i32, int32_t shift);
504 typedef void ShiftFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32);
505
506 /**
507 * arm_tbflags_from_tb:
508 * @tb: the TranslationBlock
509 *
510 * Extract the flag values from @tb.
511 */
arm_tbflags_from_tb(const TranslationBlock * tb)512 static inline CPUARMTBFlags arm_tbflags_from_tb(const TranslationBlock *tb)
513 {
514 return (CPUARMTBFlags){ tb->flags, tb->cs_base };
515 }
516
517 /*
518 * Enum for argument to fpstatus_ptr().
519 */
520 typedef enum ARMFPStatusFlavour {
521 FPST_FPCR,
522 FPST_FPCR_F16,
523 FPST_STD,
524 FPST_STD_F16,
525 } ARMFPStatusFlavour;
526
527 /**
528 * fpstatus_ptr: return TCGv_ptr to the specified fp_status field
529 *
530 * We have multiple softfloat float_status fields in the Arm CPU state struct
531 * (see the comment in cpu.h for details). Return a TCGv_ptr which has
532 * been set up to point to the requested field in the CPU state struct.
533 * The options are:
534 *
535 * FPST_FPCR
536 * for non-FP16 operations controlled by the FPCR
537 * FPST_FPCR_F16
538 * for operations controlled by the FPCR where FPCR.FZ16 is to be used
539 * FPST_STD
540 * for A32/T32 Neon operations using the "standard FPSCR value"
541 * FPST_STD_F16
542 * as FPST_STD, but where FPCR.FZ16 is to be used
543 */
fpstatus_ptr(ARMFPStatusFlavour flavour)544 static inline TCGv_ptr fpstatus_ptr(ARMFPStatusFlavour flavour)
545 {
546 TCGv_ptr statusptr = tcg_temp_new_ptr();
547 int offset;
548
549 switch (flavour) {
550 case FPST_FPCR:
551 offset = offsetof(CPUARMState, vfp.fp_status);
552 break;
553 case FPST_FPCR_F16:
554 offset = offsetof(CPUARMState, vfp.fp_status_f16);
555 break;
556 case FPST_STD:
557 offset = offsetof(CPUARMState, vfp.standard_fp_status);
558 break;
559 case FPST_STD_F16:
560 offset = offsetof(CPUARMState, vfp.standard_fp_status_f16);
561 break;
562 default:
563 g_assert_not_reached();
564 }
565 tcg_gen_addi_ptr(statusptr, tcg_env, offset);
566 return statusptr;
567 }
568
569 /**
570 * finalize_memop_atom:
571 * @s: DisasContext
572 * @opc: size+sign+align of the memory operation
573 * @atom: atomicity of the memory operation
574 *
575 * Build the complete MemOp for a memory operation, including alignment,
576 * endianness, and atomicity.
577 *
578 * If (op & MO_AMASK) then the operation already contains the required
579 * alignment, e.g. for AccType_ATOMIC. Otherwise, this an optionally
580 * unaligned operation, e.g. for AccType_NORMAL.
581 *
582 * In the latter case, there are configuration bits that require alignment,
583 * and this is applied here. Note that there is no way to indicate that
584 * no alignment should ever be enforced; this must be handled manually.
585 */
finalize_memop_atom(DisasContext * s,MemOp opc,MemOp atom)586 static inline MemOp finalize_memop_atom(DisasContext *s, MemOp opc, MemOp atom)
587 {
588 if (s->align_mem && !(opc & MO_AMASK)) {
589 opc |= MO_ALIGN;
590 }
591 return opc | atom | s->be_data;
592 }
593
594 /**
595 * finalize_memop:
596 * @s: DisasContext
597 * @opc: size+sign+align of the memory operation
598 *
599 * Like finalize_memop_atom, but with default atomicity.
600 */
finalize_memop(DisasContext * s,MemOp opc)601 static inline MemOp finalize_memop(DisasContext *s, MemOp opc)
602 {
603 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16 : MO_ATOM_IFALIGN;
604 return finalize_memop_atom(s, opc, atom);
605 }
606
607 /**
608 * finalize_memop_pair:
609 * @s: DisasContext
610 * @opc: size+sign+align of the memory operation
611 *
612 * Like finalize_memop_atom, but with atomicity for a pair.
613 * C.f. Pseudocode for Mem[], operand ispair.
614 */
finalize_memop_pair(DisasContext * s,MemOp opc)615 static inline MemOp finalize_memop_pair(DisasContext *s, MemOp opc)
616 {
617 MemOp atom = s->lse2 ? MO_ATOM_WITHIN16_PAIR : MO_ATOM_IFALIGN_PAIR;
618 return finalize_memop_atom(s, opc, atom);
619 }
620
621 /**
622 * finalize_memop_asimd:
623 * @s: DisasContext
624 * @opc: size+sign+align of the memory operation
625 *
626 * Like finalize_memop_atom, but with atomicity of AccessType_ASIMD.
627 */
finalize_memop_asimd(DisasContext * s,MemOp opc)628 static inline MemOp finalize_memop_asimd(DisasContext *s, MemOp opc)
629 {
630 /*
631 * In the pseudocode for Mem[], with AccessType_ASIMD, size == 16,
632 * if IsAligned(8), the first case provides separate atomicity for
633 * the pair of 64-bit accesses. If !IsAligned(8), the middle cases
634 * do not apply, and we're left with the final case of no atomicity.
635 * Thus MO_ATOM_IFALIGN_PAIR.
636 *
637 * For other sizes, normal LSE2 rules apply.
638 */
639 if ((opc & MO_SIZE) == MO_128) {
640 return finalize_memop_atom(s, opc, MO_ATOM_IFALIGN_PAIR);
641 }
642 return finalize_memop(s, opc);
643 }
644
645 /**
646 * asimd_imm_const: Expand an encoded SIMD constant value
647 *
648 * Expand a SIMD constant value. This is essentially the pseudocode
649 * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for
650 * VMVN and VBIC (when cmode < 14 && op == 1).
651 *
652 * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;
653 * callers must catch this; we return the 64-bit constant value defined
654 * for AArch64.
655 *
656 * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but
657 * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;
658 * we produce an immediate constant value of 0 in these cases.
659 */
660 uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);
661
662 /*
663 * gen_disas_label:
664 * Create a label and cache a copy of pc_save.
665 */
gen_disas_label(DisasContext * s)666 static inline DisasLabel gen_disas_label(DisasContext *s)
667 {
668 return (DisasLabel){
669 .label = gen_new_label(),
670 .pc_save = s->pc_save,
671 };
672 }
673
674 /*
675 * set_disas_label:
676 * Emit a label and restore the cached copy of pc_save.
677 */
set_disas_label(DisasContext * s,DisasLabel l)678 static inline void set_disas_label(DisasContext *s, DisasLabel l)
679 {
680 gen_set_label(l.label);
681 s->pc_save = l.pc_save;
682 }
683
gen_lookup_cp_reg(uint32_t key)684 static inline TCGv_ptr gen_lookup_cp_reg(uint32_t key)
685 {
686 TCGv_ptr ret = tcg_temp_new_ptr();
687 gen_helper_lookup_cp_reg(ret, tcg_env, tcg_constant_i32(key));
688 return ret;
689 }
690
691 /*
692 * Set and reset rounding mode around another operation.
693 */
gen_set_rmode(ARMFPRounding rmode,TCGv_ptr fpst)694 static inline TCGv_i32 gen_set_rmode(ARMFPRounding rmode, TCGv_ptr fpst)
695 {
696 TCGv_i32 new = tcg_constant_i32(arm_rmode_to_sf(rmode));
697 TCGv_i32 old = tcg_temp_new_i32();
698
699 gen_helper_set_rmode(old, new, fpst);
700 return old;
701 }
702
gen_restore_rmode(TCGv_i32 old,TCGv_ptr fpst)703 static inline void gen_restore_rmode(TCGv_i32 old, TCGv_ptr fpst)
704 {
705 gen_helper_set_rmode(old, old, fpst);
706 }
707
708 /*
709 * Helpers for implementing sets of trans_* functions.
710 * Defer the implementation of NAME to FUNC, with optional extra arguments.
711 */
712 #define TRANS(NAME, FUNC, ...) \
713 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
714 { return FUNC(s, __VA_ARGS__); }
715 #define TRANS_FEAT(NAME, FEAT, FUNC, ...) \
716 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
717 { return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); }
718
719 #define TRANS_FEAT_NONSTREAMING(NAME, FEAT, FUNC, ...) \
720 static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
721 { \
722 s->is_nonstreaming = true; \
723 return dc_isar_feature(FEAT, s) && FUNC(s, __VA_ARGS__); \
724 }
725
726 #endif /* TARGET_ARM_TRANSLATE_H */
727