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Searched refs:t0 (Results 1 – 25 of 96) sorted by relevance

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/openbmc/u-boot/board/imgtec/malta/
H A Dlowlevel_init.S31 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
32 lw t0, 0(t0)
33 srl t0, t0, MALTA_REVISION_CORID_SHF
34 andi t0, t0, (MALTA_REVISION_CORID_MSK >> \
39 beq t0, t1, _gt64120
43 beq t0, t1, _msc01
66 li t0, CPU_TO_GT32(0xdf000000)
67 sw t0, GT_ISD_OFS(t1)
73 li t0, CPU_TO_GT32(0xc0000000)
74 sw t0, GT_PCI0IOLD_OFS(t1)
[all …]
/openbmc/qemu/target/mips/tcg/
H A Docteon_translate.c28 TCGv t0 = tcg_temp_new(); in trans_BBIT() local
29 gen_load_gpr(t0, a->rs); in trans_BBIT()
33 tcg_gen_and_tl(bcond, p, t0); in trans_BBIT()
35 tcg_gen_andc_tl(bcond, p, t0); in trans_BBIT()
46 TCGv t0, t1; in trans_BADDU() local
53 t0 = tcg_temp_new(); in trans_BADDU()
55 gen_load_gpr(t0, a->rs); in trans_BADDU()
58 tcg_gen_add_tl(t0, t0, t1); in trans_BADDU()
59 tcg_gen_andi_i64(cpu_gpr[a->rd], t0, 0xff); in trans_BADDU()
65 TCGv t0, t1; in trans_DMUL() local
[all …]
H A Dmxu_translate.c674 TCGv t0; in gen_mxu_s32i2m() local
677 t0 = tcg_temp_new(); in gen_mxu_s32i2m()
682 gen_load_gpr(t0, Rb); in gen_mxu_s32i2m()
684 gen_store_mxu_gpr(t0, XRa); in gen_mxu_s32i2m()
686 gen_store_mxu_cr(t0); in gen_mxu_s32i2m()
695 TCGv t0; in gen_mxu_s32m2i() local
698 t0 = tcg_temp_new(); in gen_mxu_s32m2i()
704 gen_load_mxu_gpr(t0, XRa); in gen_mxu_s32m2i()
706 gen_load_mxu_cr(t0); in gen_mxu_s32m2i()
709 gen_store_gpr(t0, Rb); in gen_mxu_s32m2i()
[all …]
H A Dtranslate_addr_const.c18 TCGv t0; in gen_lsa() local
25 t0 = tcg_temp_new(); in gen_lsa()
27 gen_load_gpr(t0, rs); in gen_lsa()
29 tcg_gen_shli_tl(t0, t0, sa); in gen_lsa()
30 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_lsa()
37 TCGv t0; in gen_dlsa() local
46 t0 = tcg_temp_new(); in gen_dlsa()
48 gen_load_gpr(t0, rs); in gen_dlsa()
50 tcg_gen_shli_tl(t0, t0, sa); in gen_dlsa()
51 tcg_gen_add_tl(cpu_gpr[rd], t0, t1); in gen_dlsa()
H A Dloong_translate.c31 TCGv t0, t1; in gen_lext_DIV_G() local
39 t0 = tcg_temp_new(); in gen_lext_DIV_G()
45 gen_load_gpr(t0, rs); in gen_lext_DIV_G()
49 tcg_gen_ext32s_tl(t0, t0); in gen_lext_DIV_G()
57 tcg_gen_brcondi_tl(TCG_COND_NE, t0, is_double ? LLONG_MIN : INT_MIN, l2); in gen_lext_DIV_G()
59 tcg_gen_mov_tl(cpu_gpr[rd], t0); in gen_lext_DIV_G()
63 tcg_gen_div_tl(cpu_gpr[rd], t0, t1); in gen_lext_DIV_G()
85 TCGv t0, t1; in gen_lext_DIVU_G() local
93 t0 = tcg_temp_new(); in gen_lext_DIVU_G()
98 gen_load_gpr(t0, rs); in gen_lext_DIVU_G()
[all …]
H A Dtx79_translate.c237 TCGv_i64 c0, c1, ax, bx, t0, t1, t2; in trans_parallel_compare() local
248 t0 = tcg_temp_new_i64(); in trans_parallel_compare()
256 tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); in trans_parallel_compare()
258 tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); in trans_parallel_compare()
265 tcg_gen_sextract_i64(t0, ax, wlen * i, wlen); in trans_parallel_compare()
267 tcg_gen_movcond_i64(cond, t2, t1, t0, c1, c0); in trans_parallel_compare()
324 TCGv_i64 t0; in trans_LQ() local
332 t0 = tcg_temp_new_i64(); in trans_LQ()
343 tcg_gen_qemu_ld_i64(t0, addr, ctx->mem_idx, mo_endian(ctx) | MO_UQ); in trans_LQ()
344 gen_store_gpr(t0, a->rt); in trans_LQ()
[all …]
/openbmc/u-boot/arch/mips/mach-jz47xx/
H A Dstart.S27 mfc0 t0, CP0_CONFIG, 7
29 ori t0, 2
30 mtc0 t0, CP0_CONFIG, 7
36 li t0, 0x0040FC04
37 mtc0 t0, CP0_STATUS
46 la t0, CPM_BASE
47 lw t1, 0x24(t0)
49 sw t1, 0x24(t0)
66 li t0, KSEG0
67 addu t1, t0, CONFIG_SYS_DCACHE_SIZE
[all …]
/openbmc/u-boot/arch/mips/lib/
H A Dcache_init.S120 mfc0 t0, CP0_CONFIG, 1
121 bgez t0, l2_probe_done
131 mfc0 t0, CP0_CONFIG, 2
132 bgez t0, l2_probe_cop0
133 mfc0 t0, CP0_CONFIG, 3
134 bgez t0, l2_probe_cop0
135 mfc0 t0, CP0_CONFIG, 4
136 bgez t0, l2_probe_cop0
139 mfc0 t0, CP0_CONFIG, 5
140 and R_L2_L2C, t0, MIPS_CONF5_L2C
[all …]
/openbmc/u-boot/arch/mips/cpu/
H A Dcm_init.S16 mfc0 t0, CP0_CONFIG, 1
17 bgez t0, 2f
18 mfc0 t0, CP0_CONFIG, 2
19 bgez t0, 2f
22 mfc0 t0, CP0_CONFIG, 3
23 and t0, t0, MIPS_CONF3_CMGCR
24 beqz t0, 2f
27 1: MFC0 t0, CP0_CMGCRBASE
28 PTR_SLL t0, t0, 4
32 beq t0, t1, 2f
[all …]
H A Dstart.S41 mfc0 t0, CP0_WATCHHI,\sel
42 bgez t0, wr_done
55 li t0, -16
57 and sp, t1, t0 # force 16 byte alignment
60 and sp, sp, t0 # force 16 byte alignment
66 and sp, sp, t0 # force 16 byte alignment
71 move t0, k0
73 PTR_S zero, 0(t0)
74 blt t0, t1, 1b
75 PTR_ADDIU t0, PTRSIZE
[all …]
/openbmc/u-boot/arch/riscv/cpu/
H A Dstart.S42 la t0, trap_entry
43 csrw MODE_PREFIX(tvec), t0
56 li t0, -16
58 and sp, t1, t0 /* force 16 byte alignment */
69 la t0, prior_stage_fdt_address
70 SREG s1, 0(t0)
99 la t0, _start
100 sub t6, s4, t0 /* t6 <- relocation offset */
101 beq t0, s4, clear_bss /* skip relocation */
105 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
[all …]
/openbmc/qemu/tests/tcg/loongarch64/system/
H A Dboot.S13 la.local t0, stack_end
14 move sp, t0
24 li.w t0, 0x34
26 st.b t0, t1, 0
39 ori t0, t2, 0x1e5
40 ld.bu t0, t0, 0
41 andi t0, t0, 0x20
42 ext.w.b t0, t0
43 bnez t0, in
48 lu12i.w t0, 0x1fe00
[all …]
/openbmc/qemu/target/sh4/
H A Dop_helper.c254 float32 helper_fadd_FT(CPUSH4State *env, float32 t0, float32 t1) in helper_fadd_FT() argument
257 t0 = float32_add(t0, t1, &env->fp_status); in helper_fadd_FT()
259 return t0; in helper_fadd_FT()
262 float64 helper_fadd_DT(CPUSH4State *env, float64 t0, float64 t1) in helper_fadd_DT() argument
265 t0 = float64_add(t0, t1, &env->fp_status); in helper_fadd_DT()
267 return t0; in helper_fadd_DT()
270 uint32_t helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1) in helper_fcmp_eq_FT() argument
275 relation = float32_compare(t0, t1, &env->fp_status); in helper_fcmp_eq_FT()
280 uint32_t helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1) in helper_fcmp_eq_DT() argument
285 relation = float64_compare(t0, t1, &env->fp_status); in helper_fcmp_eq_DT()
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S81 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
82 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
84 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
86 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
89 sw t1, AR933X_RESET_REG_RESET_MODULE(t0)
100 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
106 sw t1, AR933X_RESET_REG_BOOTSTRAP(t0)
110 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
112 sw t1, AR933X_RTC_REG_FORCE_WAKE(t0)
118 sw t1, AR933X_RTC_REG_RESET(t0)
[all …]
/openbmc/qemu/tests/tcg/riscv64/
H A Dtest-mepc-masking.S15 lla t0, machine_trap_handler
16 csrw mtvec, t0
19 li t0, 0x80004001
20 csrw stvec, t0
36 csrr t0, mcause
38 bne t0, t1, skip_test
41 csrr t0, stvec /* t0 = 0x80004001 */
42 csrw mepc, t0 /* Write to MEPC */
49 lla t0, test_completed
50 csrw mepc, t0
[all …]
H A Dissue1060.S6 lla t0, trap
7 csrw mtvec, t0
22 csrr t0, mepc
24 lwu t2, 0(t0)
28 addi t0, t0, 4
29 csrw mepc, t0
38 li t0, 0x20026 # ADP_Stopped_ApplicationExit
39 sd t0, 0(a1)
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_shift.c.inc8 TCGv t0 = tcg_temp_new();
9 tcg_gen_andi_tl(t0, src2, 0x1f);
10 tcg_gen_shl_tl(dest, src1, t0);
15 TCGv t0 = tcg_temp_new();
16 tcg_gen_andi_tl(t0, src2, 0x1f);
17 tcg_gen_shr_tl(dest, src1, t0);
22 TCGv t0 = tcg_temp_new();
23 tcg_gen_andi_tl(t0, src2, 0x1f);
24 tcg_gen_sar_tl(dest, src1, t0);
29 TCGv t0 = tcg_temp_new();
[all …]
H A Dtrans_bit.c.inc117 TCGv t0 = tcg_temp_new();
120 tcg_gen_shri_tl(t0, src1, 8);
121 tcg_gen_and_tl(t0, t0, mask);
124 tcg_gen_or_tl(dest, t0, t1);
130 TCGv t0 = tcg_temp_new();
133 tcg_gen_shri_tl(t0, src1, 8);
134 tcg_gen_and_tl(t0, t0, mask);
137 tcg_gen_or_tl(dest, t0, t1);
142 TCGv_i64 t0 = tcg_temp_new_i64();
146 tcg_gen_shri_i64(t0, src1, 16);
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S101 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
102 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
105 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
107 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
110 sw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
114 li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
116 sw t1, QCA953X_RTC_REG_SYNC_RESET(t0)
122 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
127 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
129 sw t1, QCA953X_SRIF_BB_DPLL2_REG(t0)
[all …]
/openbmc/qemu/target/ppc/translate/
H A Dspe-impl.c.inc84 TCGv_i32 t0; \
89 t0 = tcg_temp_new_i32(); \
91 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
92 tcg_opi(t0, t0, rB(ctx->opcode)); \
93 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); \
95 tcg_gen_trunc_tl_i32(t0, cpu_gprh[rA(ctx->opcode)]); \
96 tcg_opi(t0, t0, rB(ctx->opcode)); \
97 tcg_gen_extu_i32_tl(cpu_gprh[rD(ctx->opcode)], t0); \
108 TCGv_i32 t0; \
113 t0 = tcg_temp_new_i32(); \
[all …]
/openbmc/u-boot/arch/mips/mach-mt7620/
H A Dlowlevel_init.S80 la t0, MT76XX_CLKCFG0_REG
81 lw t3, 0(t0)
83 sw t3, 0(t0)
87 la t0, MT76XX_CLKCFG0_REG
88 lw t1, 0(t0)
92 sw t1, 0(t0)
93 la t0, MT76XX_DYN_CFG0_REG
94 lw t3, 0(t0)
99 sw t3, 0(t0)
100 la t0, MT76XX_CLKCFG0_REG
[all …]
/openbmc/qemu/host/include/aarch64/host/
H A Dbufferiszero.c.inc17 uint32x4_t t0, t1, t2, t3;
24 t0 = vld1q_u32(buf) | vld1q_u32(buf + len - 16);
30 t0 |= e[-1];
31 REASSOC_BARRIER(t0, t1);
33 t0 |= t1;
35 REASSOC_BARRIER(t0, t2);
36 t0 |= t2;
48 if (unlikely(vmaxvq_u32(t0) != 0)) {
52 t0 = p[0] | p[1];
56 REASSOC_BARRIER(t0, t1);
[all …]
/openbmc/qemu/crypto/
H A Daes.c1451 u32 s0, s1, s2, s3, t0, t1, t2, t3; in AES_encrypt() local
1469 …t0 = AES_Te0[s0 >> 24] ^ AES_Te1[(s1 >> 16) & 0xff] ^ AES_Te2[(s2 >> 8) & 0xff] ^ AES_Te3[s3 & 0x… in AES_encrypt()
1474 …s0 = AES_Te0[t0 >> 24] ^ AES_Te1[(t1 >> 16) & 0xff] ^ AES_Te2[(t2 >> 8) & 0xff] ^ AES_Te3[t3 & 0x… in AES_encrypt()
1475 …[t1 >> 24] ^ AES_Te1[(t2 >> 16) & 0xff] ^ AES_Te2[(t3 >> 8) & 0xff] ^ AES_Te3[t0 & 0xff] ^ rk[ 9]; in AES_encrypt()
1476 …s2 = AES_Te0[t2 >> 24] ^ AES_Te1[(t3 >> 16) & 0xff] ^ AES_Te2[(t0 >> 8) & 0xff] ^ AES_Te3[t1 & 0x… in AES_encrypt()
1477 …s3 = AES_Te0[t3 >> 24] ^ AES_Te1[(t0 >> 16) & 0xff] ^ AES_Te2[(t1 >> 8) & 0xff] ^ AES_Te3[t2 & 0x… in AES_encrypt()
1479 …t0 = AES_Te0[s0 >> 24] ^ AES_Te1[(s1 >> 16) & 0xff] ^ AES_Te2[(s2 >> 8) & 0xff] ^ AES_Te3[s3 & 0x… in AES_encrypt()
1484 …s0 = AES_Te0[t0 >> 24] ^ AES_Te1[(t1 >> 16) & 0xff] ^ AES_Te2[(t2 >> 8) & 0xff] ^ AES_Te3[t3 & 0x… in AES_encrypt()
1485 …[t1 >> 24] ^ AES_Te1[(t2 >> 16) & 0xff] ^ AES_Te2[(t3 >> 8) & 0xff] ^ AES_Te3[t0 & 0xff] ^ rk[17]; in AES_encrypt()
1486 …s2 = AES_Te0[t2 >> 24] ^ AES_Te1[(t3 >> 16) & 0xff] ^ AES_Te2[(t0 >> 8) & 0xff] ^ AES_Te3[t1 & 0x… in AES_encrypt()
[all …]
/openbmc/qemu/docs/devel/
H A Dtcg-ops.rst62 add_i32 t0, t1, t2 /* (t0 <- t1 + t2) */
193 and_i32 t0, t0, $0xffffffff
207 add_i32 t0, t1, t2
208 add_i32 t0, t0, $1
209 mov_i32 t0, $1
242 * - brcond *t0*, *t1*, *cond*, *label*
244 - | Conditional jump if *t0* *cond* *t1* is true. *cond* can be:
264 * - add *t0*, *t1*, *t2*
266 - | *t0* = *t1* + *t2*
268 * - sub *t0*, *t1*, *t2*
[all …]
/openbmc/qemu/target/riscv/
H A Dzce_helper.c39 target_ulong t0; in HELPER() local
46 t0 = base + (index << 2); in HELPER()
47 target = cpu_ldl_code(env, t0); in HELPER()
49 t0 = base + (index << 3); in HELPER()
50 target = cpu_ldq_code(env, t0); in HELPER()

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