1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0 */ 27a9d109bSPaul Burton/* 37a9d109bSPaul Burton * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> 47a9d109bSPaul Burton */ 57a9d109bSPaul Burton 67a9d109bSPaul Burton#include <config.h> 77a9d109bSPaul Burton#include <gt64120.h> 8baf37f06SPaul Burton#include <msc01.h> 9baf37f06SPaul Burton#include <pci.h> 107a9d109bSPaul Burton 117a9d109bSPaul Burton#include <asm/addrspace.h> 120f832b9cSPaul Burton#include <asm/asm.h> 137a9d109bSPaul Burton#include <asm/regdef.h> 147a9d109bSPaul Burton#include <asm/malta.h> 15e174bd74SPaul Burton#include <asm/mipsregs.h> 167a9d109bSPaul Burton 177a9d109bSPaul Burton#ifdef CONFIG_SYS_BIG_ENDIAN 187a9d109bSPaul Burton#define CPU_TO_GT32(_x) ((_x)) 197a9d109bSPaul Burton#else 207a9d109bSPaul Burton#define CPU_TO_GT32(_x) ( \ 217a9d109bSPaul Burton (((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \ 227a9d109bSPaul Burton (((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24)) 237a9d109bSPaul Burton#endif 247a9d109bSPaul Burton 257a9d109bSPaul Burton .text 267a9d109bSPaul Burton .set noreorder 277a9d109bSPaul Burton 287a9d109bSPaul Burton .globl lowlevel_init 297a9d109bSPaul Burtonlowlevel_init: 30baf37f06SPaul Burton /* detect the core card */ 310f832b9cSPaul Burton PTR_LI t0, CKSEG1ADDR(MALTA_REVISION) 32baf37f06SPaul Burton lw t0, 0(t0) 33baf37f06SPaul Burton srl t0, t0, MALTA_REVISION_CORID_SHF 34baf37f06SPaul Burton andi t0, t0, (MALTA_REVISION_CORID_MSK >> \ 35baf37f06SPaul Burton MALTA_REVISION_CORID_SHF) 36baf37f06SPaul Burton 37baf37f06SPaul Burton /* core cards using the gt64120 system controller */ 38baf37f06SPaul Burton li t1, MALTA_REVISION_CORID_CORE_LV 39baf37f06SPaul Burton beq t0, t1, _gt64120 40baf37f06SPaul Burton 41baf37f06SPaul Burton /* core cards using the MSC01 system controller */ 42baf37f06SPaul Burton li t1, MALTA_REVISION_CORID_CORE_FPGA6 43baf37f06SPaul Burton beq t0, t1, _msc01 44baf37f06SPaul Burton nop 45baf37f06SPaul Burton 46baf37f06SPaul Burton /* unknown system controller */ 47baf37f06SPaul Burton b . 48baf37f06SPaul Burton nop 497a9d109bSPaul Burton 507a9d109bSPaul Burton /* 517a9d109bSPaul Burton * Load BAR registers of GT64120 as done by YAMON 527a9d109bSPaul Burton * 537a9d109bSPaul Burton * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com> 547a9d109bSPaul Burton * to the barebox mailing list. 557a9d109bSPaul Burton * The subject of the original patch: 567a9d109bSPaul Burton * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map' 577a9d109bSPaul Burton * URL: 587a9d109bSPaul Burton * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html 597a9d109bSPaul Burton * 607a9d109bSPaul Burton * based on write_bootloader() in qemu.git/hw/mips_malta.c 617a9d109bSPaul Burton * see GT64120 manual and qemu.git/hw/gt64xxx.c for details 627a9d109bSPaul Burton */ 63baf37f06SPaul Burton_gt64120: 647a9d109bSPaul Burton /* move GT64120 registers from 0x14000000 to 0x1be00000 */ 650f832b9cSPaul Burton PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE) 667a9d109bSPaul Burton li t0, CPU_TO_GT32(0xdf000000) 677a9d109bSPaul Burton sw t0, GT_ISD_OFS(t1) 687a9d109bSPaul Burton 697a9d109bSPaul Burton /* setup MEM-to-PCI0 mapping */ 700f832b9cSPaul Burton PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE) 717a9d109bSPaul Burton 727a9d109bSPaul Burton /* setup PCI0 io window to 0x18000000-0x181fffff */ 737a9d109bSPaul Burton li t0, CPU_TO_GT32(0xc0000000) 747a9d109bSPaul Burton sw t0, GT_PCI0IOLD_OFS(t1) 757a9d109bSPaul Burton li t0, CPU_TO_GT32(0x40000000) 767a9d109bSPaul Burton sw t0, GT_PCI0IOHD_OFS(t1) 777a9d109bSPaul Burton 787a9d109bSPaul Burton /* setup PCI0 mem windows */ 797a9d109bSPaul Burton li t0, CPU_TO_GT32(0x80000000) 807a9d109bSPaul Burton sw t0, GT_PCI0M0LD_OFS(t1) 817a9d109bSPaul Burton li t0, CPU_TO_GT32(0x3f000000) 827a9d109bSPaul Burton sw t0, GT_PCI0M0HD_OFS(t1) 837a9d109bSPaul Burton 847a9d109bSPaul Burton li t0, CPU_TO_GT32(0xc1000000) 857a9d109bSPaul Burton sw t0, GT_PCI0M1LD_OFS(t1) 867a9d109bSPaul Burton li t0, CPU_TO_GT32(0x5e000000) 877a9d109bSPaul Burton sw t0, GT_PCI0M1HD_OFS(t1) 887a9d109bSPaul Burton 897a9d109bSPaul Burton jr ra 907a9d109bSPaul Burton nop 91baf37f06SPaul Burton 92baf37f06SPaul Burton /* 93baf37f06SPaul Burton * 94baf37f06SPaul Burton */ 95baf37f06SPaul Burton_msc01: 96baf37f06SPaul Burton /* setup peripheral bus controller clock divide */ 970f832b9cSPaul Burton PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE) 98baf37f06SPaul Burton li t1, 0x1 << MSC01_PBC_CLKCFG_SHF 99baf37f06SPaul Burton sw t1, MSC01_PBC_CLKCFG_OFS(t0) 100baf37f06SPaul Burton 101baf37f06SPaul Burton /* tweak peripheral bus controller timings */ 102baf37f06SPaul Burton li t1, (0x1 << MSC01_PBC_CS0TIM_CDT_SHF) | \ 103baf37f06SPaul Burton (0x1 << MSC01_PBC_CS0TIM_CAT_SHF) 104baf37f06SPaul Burton sw t1, MSC01_PBC_CS0TIM_OFS(t0) 105baf37f06SPaul Burton li t1, (0x0 << MSC01_PBC_CS0RW_RDT_SHF) | \ 106baf37f06SPaul Burton (0x2 << MSC01_PBC_CS0RW_RAT_SHF) | \ 107baf37f06SPaul Burton (0x0 << MSC01_PBC_CS0RW_WDT_SHF) | \ 108baf37f06SPaul Burton (0x2 << MSC01_PBC_CS0RW_WAT_SHF) 109baf37f06SPaul Burton sw t1, MSC01_PBC_CS0RW_OFS(t0) 110baf37f06SPaul Burton lw t1, MSC01_PBC_CS0CFG_OFS(t0) 111baf37f06SPaul Burton li t2, MSC01_PBC_CS0CFG_DTYP_MSK 112baf37f06SPaul Burton and t1, t2 113baf37f06SPaul Burton ori t1, (0x0 << MSC01_PBC_CS0CFG_ADM_SHF) | \ 114baf37f06SPaul Burton (0x3 << MSC01_PBC_CS0CFG_WSIDLE_SHF) | \ 115baf37f06SPaul Burton (0x10 << MSC01_PBC_CS0CFG_WS_SHF) 116baf37f06SPaul Burton sw t1, MSC01_PBC_CS0CFG_OFS(t0) 117baf37f06SPaul Burton 118baf37f06SPaul Burton /* setup basic address decode */ 1190f832b9cSPaul Burton PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE) 120baf37f06SPaul Burton li t1, 0x0 121baf37f06SPaul Burton li t2, -CONFIG_SYS_MEM_SIZE 122baf37f06SPaul Burton sw t1, MSC01_BIU_MCBAS1L_OFS(t0) 123baf37f06SPaul Burton sw t2, MSC01_BIU_MCMSK1L_OFS(t0) 124baf37f06SPaul Burton sw t1, MSC01_BIU_MCBAS2L_OFS(t0) 125baf37f06SPaul Burton sw t2, MSC01_BIU_MCMSK2L_OFS(t0) 126baf37f06SPaul Burton 127baf37f06SPaul Burton /* initialise IP1 - unused */ 128baf37f06SPaul Burton li t1, MALTA_MSC01_IP1_BASE 129baf37f06SPaul Burton li t2, -MALTA_MSC01_IP1_SIZE 130baf37f06SPaul Burton sw t1, MSC01_BIU_IP1BAS1L_OFS(t0) 131baf37f06SPaul Burton sw t2, MSC01_BIU_IP1MSK1L_OFS(t0) 132baf37f06SPaul Burton sw t1, MSC01_BIU_IP1BAS2L_OFS(t0) 133baf37f06SPaul Burton sw t2, MSC01_BIU_IP1MSK2L_OFS(t0) 134baf37f06SPaul Burton 135baf37f06SPaul Burton /* initialise IP2 - PCI */ 136baf37f06SPaul Burton li t1, MALTA_MSC01_IP2_BASE1 137baf37f06SPaul Burton li t2, -MALTA_MSC01_IP2_SIZE1 138baf37f06SPaul Burton sw t1, MSC01_BIU_IP2BAS1L_OFS(t0) 139baf37f06SPaul Burton sw t2, MSC01_BIU_IP2MSK1L_OFS(t0) 140baf37f06SPaul Burton li t1, MALTA_MSC01_IP2_BASE2 141baf37f06SPaul Burton li t2, -MALTA_MSC01_IP2_SIZE2 142baf37f06SPaul Burton sw t1, MSC01_BIU_IP2BAS2L_OFS(t0) 143baf37f06SPaul Burton sw t2, MSC01_BIU_IP2MSK2L_OFS(t0) 144baf37f06SPaul Burton 145baf37f06SPaul Burton /* initialise IP3 - peripheral bus controller */ 146baf37f06SPaul Burton li t1, MALTA_MSC01_IP3_BASE 147baf37f06SPaul Burton li t2, -MALTA_MSC01_IP3_SIZE 148baf37f06SPaul Burton sw t1, MSC01_BIU_IP3BAS1L_OFS(t0) 149baf37f06SPaul Burton sw t2, MSC01_BIU_IP3MSK1L_OFS(t0) 150baf37f06SPaul Burton sw t1, MSC01_BIU_IP3BAS2L_OFS(t0) 151baf37f06SPaul Burton sw t2, MSC01_BIU_IP3MSK2L_OFS(t0) 152baf37f06SPaul Burton 153baf37f06SPaul Burton /* setup PCI memory */ 1540f832b9cSPaul Burton PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE) 155baf37f06SPaul Burton li t1, MALTA_MSC01_PCIMEM_BASE 156baf37f06SPaul Burton li t2, (-MALTA_MSC01_PCIMEM_SIZE) & MSC01_PCI_SC2PMMSKL_MSK_MSK 157baf37f06SPaul Burton li t3, MALTA_MSC01_PCIMEM_MAP 158baf37f06SPaul Burton sw t1, MSC01_PCI_SC2PMBASL_OFS(t0) 159baf37f06SPaul Burton sw t2, MSC01_PCI_SC2PMMSKL_OFS(t0) 160baf37f06SPaul Burton sw t3, MSC01_PCI_SC2PMMAPL_OFS(t0) 161baf37f06SPaul Burton 162baf37f06SPaul Burton /* setup PCI I/O */ 163baf37f06SPaul Burton li t1, MALTA_MSC01_PCIIO_BASE 164baf37f06SPaul Burton li t2, (-MALTA_MSC01_PCIIO_SIZE) & MSC01_PCI_SC2PIOMSKL_MSK_MSK 165baf37f06SPaul Burton li t3, MALTA_MSC01_PCIIO_MAP 166baf37f06SPaul Burton sw t1, MSC01_PCI_SC2PIOBASL_OFS(t0) 167baf37f06SPaul Burton sw t2, MSC01_PCI_SC2PIOMSKL_OFS(t0) 168baf37f06SPaul Burton sw t3, MSC01_PCI_SC2PIOMAPL_OFS(t0) 169baf37f06SPaul Burton 170baf37f06SPaul Burton /* setup PCI_BAR0 memory window */ 171baf37f06SPaul Burton li t1, -CONFIG_SYS_MEM_SIZE 172baf37f06SPaul Burton sw t1, MSC01_PCI_BAR0_OFS(t0) 173baf37f06SPaul Burton 174baf37f06SPaul Burton /* setup PCI to SysCon/CPU translation */ 175baf37f06SPaul Burton sw t1, MSC01_PCI_P2SCMSKL_OFS(t0) 176baf37f06SPaul Burton sw zero, MSC01_PCI_P2SCMAPL_OFS(t0) 177baf37f06SPaul Burton 178baf37f06SPaul Burton /* setup PCI vendor & device IDs */ 179baf37f06SPaul Burton li t1, (PCI_VENDOR_ID_MIPS << MSC01_PCI_HEAD0_VENDORID_SHF) | \ 180baf37f06SPaul Burton (PCI_DEVICE_ID_MIPS_MSC01 << MSC01_PCI_HEAD0_DEVICEID_SHF) 181baf37f06SPaul Burton sw t1, MSC01_PCI_HEAD0_OFS(t0) 182baf37f06SPaul Burton 183baf37f06SPaul Burton /* setup PCI subsystem vendor & device IDs */ 184baf37f06SPaul Burton sw t1, MSC01_PCI_HEAD11_OFS(t0) 185baf37f06SPaul Burton 186baf37f06SPaul Burton /* setup PCI class, revision */ 187baf37f06SPaul Burton li t1, (PCI_CLASS_BRIDGE_HOST << MSC01_PCI_HEAD2_CLASS_SHF) | \ 188baf37f06SPaul Burton (0x1 << MSC01_PCI_HEAD2_REV_SHF) 189baf37f06SPaul Burton sw t1, MSC01_PCI_HEAD2_OFS(t0) 190baf37f06SPaul Burton 191baf37f06SPaul Burton /* ensure a sane setup */ 192baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD3_OFS(t0) 193baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD4_OFS(t0) 194baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD5_OFS(t0) 195baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD6_OFS(t0) 196baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD7_OFS(t0) 197baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD8_OFS(t0) 198baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD9_OFS(t0) 199baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD10_OFS(t0) 200baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD12_OFS(t0) 201baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD13_OFS(t0) 202baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD14_OFS(t0) 203baf37f06SPaul Burton sw zero, MSC01_PCI_HEAD15_OFS(t0) 204baf37f06SPaul Burton 205baf37f06SPaul Burton /* setup PCI command register */ 206baf37f06SPaul Burton li t1, (PCI_COMMAND_FAST_BACK | \ 207baf37f06SPaul Burton PCI_COMMAND_SERR | \ 208baf37f06SPaul Burton PCI_COMMAND_PARITY | \ 209baf37f06SPaul Burton PCI_COMMAND_MASTER | \ 210baf37f06SPaul Burton PCI_COMMAND_MEMORY) 211baf37f06SPaul Burton sw t1, MSC01_PCI_HEAD1_OFS(t0) 212baf37f06SPaul Burton 213baf37f06SPaul Burton /* setup PCI byte swapping */ 214baf37f06SPaul Burton#ifdef CONFIG_SYS_BIG_ENDIAN 215baf37f06SPaul Burton li t1, (0x1 << MSC01_PCI_SWAP_BAR0_BSWAP_SHF) | \ 216baf37f06SPaul Burton (0x1 << MSC01_PCI_SWAP_IO_BSWAP_SHF) 217baf37f06SPaul Burton sw t1, MSC01_PCI_SWAP_OFS(t0) 218baf37f06SPaul Burton#else 219baf37f06SPaul Burton sw zero, MSC01_PCI_SWAP_OFS(t0) 220baf37f06SPaul Burton#endif 221baf37f06SPaul Burton 222baf37f06SPaul Burton /* enable PCI host configuration cycles */ 223baf37f06SPaul Burton lw t1, MSC01_PCI_CFG_OFS(t0) 224baf37f06SPaul Burton li t2, MSC01_PCI_CFG_RA_MSK | \ 225baf37f06SPaul Burton MSC01_PCI_CFG_G_MSK | \ 226baf37f06SPaul Burton MSC01_PCI_CFG_EN_MSK 227baf37f06SPaul Burton or t1, t1, t2 228baf37f06SPaul Burton sw t1, MSC01_PCI_CFG_OFS(t0) 229baf37f06SPaul Burton 230baf37f06SPaul Burton jr ra 231baf37f06SPaul Burton nop 232