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592cd5de |
| 02-Oct-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Si
Merge branch 'master' of git://git.denx.de/u-boot-spi This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
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d29a5831 |
| 29-Sep-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'mpc85xx-for-v2018.11-rc1' of git://git.denx.de/u-boot-mpc85xx Use device tree for mpc85xx with binman. Enabled for T2080QDS.
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27f622d5 |
| 29-Sep-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A.
Merge tag 'fsl-qoriq-for-v2018.11-rc1' of git://git.denx.de/u-boot-fsl-qoriq Switch to driver model for eSDHC on Layerscape SoCs including LS1021A, LS1043A, LS1046A, LS1088A, LS2088A. Switch to driver model for SATA on LS1021A and LS1043A. Add support for LS1012AFRWY rev C board. Enable SMMU for LS1043A.
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0ae8dcfe |
| 26-Sep-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot Patch queue for efi - 2018-09-26 A lot of goodness in this release. We're *very* close to running the UEFI Shell and
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot Patch queue for efi - 2018-09-26 A lot of goodness in this release. We're *very* close to running the UEFI Shell and SCT natively. The only missing piece are HII protocols. - FAT write support (needed for SCT) - improved FAT directory support (needed for SCT) - RTC support with QEMU -M virt - Sandbox support (run UEFI binaries in Linux - yay) - Proper UTF-16 support - EFI_UNICODE_COLLATION_PROTOCOL support (for UEFI Shell) - EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL support (for UEFI Shell) - Fix window size determination - Fix Tegra by explicitly unmapping RAM - Clean up handle entanglement - Lots of generic code cleanup [trini: Fixup merge conflict in include/configs/qemu-arm.h] Signed-off-by: Tom Rini <trini@konsulko.com>
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46203baf |
| 07-Sep-2018 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is n
MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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5ef337a0 |
| 07-Sep-2018 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: cache: make index base address configurable The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS syste
MIPS: cache: make index base address configurable The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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b8385860 |
| 07-Sep-2018 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: cache: optimise changing of k0 CCA mode Changing the Cache Coherency Algorithm (CCA) for kernel mode requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1 before ch
MIPS: cache: optimise changing of k0 CCA mode Changing the Cache Coherency Algorithm (CCA) for kernel mode requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1 before changing the CCA mode. Jump back to KSEG0 afterwards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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2f85c2be |
| 07-Sep-2018 |
Daniel Schwierzeck <daniel.schwierzeck@gmail.com> |
MIPS: cache: reimplement dcache_[status, enable, disable] Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when
MIPS: cache: reimplement dcache_[status, enable, disable] Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when this is required for booting an OS. Reenabling caches is much harder to implement if an optional coherency manager must be supported. As there is no real use-case anyway, dcache_enable is implemented with an error message. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
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e8f80a5a |
| 09-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-sunxi
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83d290c5 |
| 06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borro
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
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cbe7706a |
| 26-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-fsl-qoriq trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
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201c9d88 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-rockchip
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19d051a2 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-spi
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58c8c096 |
| 22-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze
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423620b9 |
| 21-Sep-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
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639200f6 |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Ensure cache ops complete in mips_cache_reset Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) be
MIPS: Ensure cache ops complete in mips_cache_reset Ensure that cache operations complete before returning from mips_cache_reset by placing a completion barrier (sync instruction) before the return. Without this there is no guarantee that the cache ops will complete before any subsequent memory accesses, since they are indexed cache ops & thus not implicitly ordered with memory accesses. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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d608254b |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Clear hazard between TagLo writes & cache ops Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache
MIPS: Clear hazard between TagLo writes & cache ops Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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7953354b |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Join the coherent domain when a CM is present MIPS Linux expects the bootloader to leave the boot CPU a member of the coherent domain when running on a system with a CM, and we wil
MIPS: Join the coherent domain when a CM is present MIPS Linux expects the bootloader to leave the boot CPU a member of the coherent domain when running on a system with a CM, and we will need to do so if we wish to make use of IOCUs to have cache-coherent DMA in U-Boot (and on some systems there is no choice in that matter). When a CM is present, join the coherent domain after completing cache initialisation. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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4baa0ab6 |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: L2 cache support This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or
MIPS: L2 cache support This patch adds support for initialising & maintaining L2 caches on MIPS systems. The L2 cache configuration may be advertised through either coprocessor 0 or the MIPS Coherence Manager depending upon the system, and support for both is included. If the L2 can be bypassed then we bypass it early in boot & initialise the L1 caches first, such that we can start making use of the L1 instruction cache as early as possible. Otherwise we initialise the L2 first such that the L1s have no opportunity to generate access to the uninitialised L2. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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5c72e5a6 |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Define register names for cache init Define names for registers holding cache sizes throughout mips_cache_reset, in order to make the code easier to read & allow for changing r
MIPS: Define register names for cache init Define names for registers holding cache sizes throughout mips_cache_reset, in order to make the code easier to read & allow for changing register assignments more easily. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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33b5c9b2 |
| 21-Sep-2016 |
Paul Burton <paul.burton@imgtec.com> |
MIPS: Enable use of the instruction cache earlier Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run fr
MIPS: Enable use of the instruction cache earlier Enable use of the instruction cache immediately after it has been initialised. This will only take effect if U-Boot was linked to run from kseg0 rather than kseg1, but when this is the case the data cache initialisation code will run cached & thus significantly faster. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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dc557e9a |
| 18-Jun-2016 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot Signed-off-by: Stefano Babic <sbabic@denx.de>
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3fc304b8 |
| 12-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://www.denx.de/git/u-boot-imx
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d77fa2ff |
| 06-Jun-2016 |
Tom Rini <trini@konsulko.com> |
Merge http://git.denx.de/u-boot-samsung Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: configs/peach-pi_defconfig configs/peach-pit_defconfig
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da6e2fab |
| 31-May-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
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