1*a1f44e0cSCharalampos Mitrodimas/* 2*a1f44e0cSCharalampos Mitrodimas * Test for MEPC masking bug fix 3*a1f44e0cSCharalampos Mitrodimas * 4*a1f44e0cSCharalampos Mitrodimas * This test verifies that MEPC properly masks the lower bits according 5*a1f44e0cSCharalampos Mitrodimas * to the RISC-V specification when vectored mode bits from STVEC are 6*a1f44e0cSCharalampos Mitrodimas * written to MEPC. 7*a1f44e0cSCharalampos Mitrodimas */ 8*a1f44e0cSCharalampos Mitrodimas 9*a1f44e0cSCharalampos Mitrodimas .option norvc 10*a1f44e0cSCharalampos Mitrodimas 11*a1f44e0cSCharalampos Mitrodimas .text 12*a1f44e0cSCharalampos Mitrodimas .global _start 13*a1f44e0cSCharalampos Mitrodimas_start: 14*a1f44e0cSCharalampos Mitrodimas /* Set up machine trap vector */ 15*a1f44e0cSCharalampos Mitrodimas lla t0, machine_trap_handler 16*a1f44e0cSCharalampos Mitrodimas csrw mtvec, t0 17*a1f44e0cSCharalampos Mitrodimas 18*a1f44e0cSCharalampos Mitrodimas /* Set STVEC with vectored mode (mode bits = 01) */ 19*a1f44e0cSCharalampos Mitrodimas li t0, 0x80004001 20*a1f44e0cSCharalampos Mitrodimas csrw stvec, t0 21*a1f44e0cSCharalampos Mitrodimas 22*a1f44e0cSCharalampos Mitrodimas /* Clear medeleg to handle exceptions in M-mode */ 23*a1f44e0cSCharalampos Mitrodimas csrw medeleg, zero 24*a1f44e0cSCharalampos Mitrodimas 25*a1f44e0cSCharalampos Mitrodimas /* Trigger illegal instruction exception */ 26*a1f44e0cSCharalampos Mitrodimas .word 0xffffffff 27*a1f44e0cSCharalampos Mitrodimas 28*a1f44e0cSCharalampos Mitrodimastest_completed: 29*a1f44e0cSCharalampos Mitrodimas /* Exit with result in a0 */ 30*a1f44e0cSCharalampos Mitrodimas /* a0 = 0: success (bits [1:0] were masked) */ 31*a1f44e0cSCharalampos Mitrodimas /* a0 != 0: failure (some bits were not masked) */ 32*a1f44e0cSCharalampos Mitrodimas j _exit 33*a1f44e0cSCharalampos Mitrodimas 34*a1f44e0cSCharalampos Mitrodimasmachine_trap_handler: 35*a1f44e0cSCharalampos Mitrodimas /* Check if illegal instruction (mcause = 2) */ 36*a1f44e0cSCharalampos Mitrodimas csrr t0, mcause 37*a1f44e0cSCharalampos Mitrodimas li t1, 2 38*a1f44e0cSCharalampos Mitrodimas bne t0, t1, skip_test 39*a1f44e0cSCharalampos Mitrodimas 40*a1f44e0cSCharalampos Mitrodimas /* Test: Copy STVEC (with mode bits) to MEPC */ 41*a1f44e0cSCharalampos Mitrodimas csrr t0, stvec /* t0 = 0x80004001 */ 42*a1f44e0cSCharalampos Mitrodimas csrw mepc, t0 /* Write to MEPC */ 43*a1f44e0cSCharalampos Mitrodimas csrr t1, mepc /* Read back MEPC */ 44*a1f44e0cSCharalampos Mitrodimas 45*a1f44e0cSCharalampos Mitrodimas /* Check if bits [1:0] are masked (IALIGN=32 without RVC) */ 46*a1f44e0cSCharalampos Mitrodimas andi a0, t1, 3 /* a0 = 0 if both bits masked correctly */ 47*a1f44e0cSCharalampos Mitrodimas 48*a1f44e0cSCharalampos Mitrodimas /* Set correct return address */ 49*a1f44e0cSCharalampos Mitrodimas lla t0, test_completed 50*a1f44e0cSCharalampos Mitrodimas csrw mepc, t0 51*a1f44e0cSCharalampos Mitrodimas 52*a1f44e0cSCharalampos Mitrodimasskip_test: 53*a1f44e0cSCharalampos Mitrodimas mret 54*a1f44e0cSCharalampos Mitrodimas 55*a1f44e0cSCharalampos Mitrodimas/* Exit with semihosting */ 56*a1f44e0cSCharalampos Mitrodimas_exit: 57*a1f44e0cSCharalampos Mitrodimas lla a1, semiargs 58*a1f44e0cSCharalampos Mitrodimas li t0, 0x20026 /* ADP_Stopped_ApplicationExit */ 59*a1f44e0cSCharalampos Mitrodimas sd t0, 0(a1) 60*a1f44e0cSCharalampos Mitrodimas sd a0, 8(a1) 61*a1f44e0cSCharalampos Mitrodimas li a0, 0x20 /* TARGET_SYS_EXIT_EXTENDED */ 62*a1f44e0cSCharalampos Mitrodimas 63*a1f44e0cSCharalampos Mitrodimas /* Semihosting call sequence */ 64*a1f44e0cSCharalampos Mitrodimas .balign 16 65*a1f44e0cSCharalampos Mitrodimas slli zero, zero, 0x1f 66*a1f44e0cSCharalampos Mitrodimas ebreak 67*a1f44e0cSCharalampos Mitrodimas srai zero, zero, 0x7 68*a1f44e0cSCharalampos Mitrodimas j . 69*a1f44e0cSCharalampos Mitrodimas 70*a1f44e0cSCharalampos Mitrodimas .data 71*a1f44e0cSCharalampos Mitrodimas .balign 8 72*a1f44e0cSCharalampos Mitrodimassemiargs: 73*a1f44e0cSCharalampos Mitrodimas .space 16 74