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Searched refs:setbits_le32 (Results 1 – 25 of 323) sorted by relevance

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/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c68 setbits_le32(&phy->ctrl, BIT(0)); in sunxi_dw_hdmi_phy_init()
70 setbits_le32(&phy->ctrl, BIT(16)); in sunxi_dw_hdmi_phy_init()
71 setbits_le32(&phy->ctrl, BIT(1)); in sunxi_dw_hdmi_phy_init()
73 setbits_le32(&phy->ctrl, BIT(2)); in sunxi_dw_hdmi_phy_init()
75 setbits_le32(&phy->ctrl, BIT(3)); in sunxi_dw_hdmi_phy_init()
80 setbits_le32(&phy->ctrl, 7 << 4); in sunxi_dw_hdmi_phy_init()
92 setbits_le32(&phy->ctrl, BIT(7)); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
174 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
188 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
[all …]
H A Dsunxi_display.c108 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI); in sunxi_hdmi_hpd_detect()
111 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE); in sunxi_hdmi_hpd_detect()
163 setbits_le32(&hdmi->ddc_ctrl, SUNXI_HMDI_DDC_CTRL_START); in sunxi_hdmi_ddc_do_command()
227 setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_DDC_GATE); in sunxi_hdmi_edid_get_mode()
356 setbits_le32(&de_fe->enable, SUNXI_DE_FE_ENABLE_EN); in sunxi_frontend_init()
462 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_ENABLE); in sunxi_composer_init()
495 setbits_le32(&de_be->mode, in sunxi_composer_mode_set()
518 setbits_le32(&de_be->mode, SUNXI_DE_BE_MODE_START); in sunxi_composer_enable()
536 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0); in sunxi_lcdc_init()
541 setbits_le32(&ccm->lvds_clk_cfg, CCM_LVDS_CTRL_RST); in sunxi_lcdc_init()
[all …]
H A Dlcdc.c46 setbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_TCON_ENABLE); in lcdc_enable()
49 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0); in lcdc_enable()
52 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_EN_MB); in lcdc_enable()
54 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVC); in lcdc_enable()
56 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0x7)); in lcdc_enable()
58 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_DRVD(0xf)); in lcdc_enable()
60 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); in lcdc_enable()
62 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT1); in lcdc_enable()
64 setbits_le32(&lcdc->lvds_ana1, SUNXI_LCDC_LVDS_ANA1_INIT2); in lcdc_enable()
65 setbits_le32(&lcdc->lvds_ana0, SUNXI_LCDC_LVDS_ANA0_UPDATE); in lcdc_enable()
[all …]
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c62 setbits_le32(RCB_REG(GCS), 1 << 5); in broadwell_pch_early_init()
100 setbits_le32(RCB_REG(0x3310), 0x0000002f); in pch_misc_init()
347 setbits_le32(RCB_REG(DEEP_SX_CONFIG), in pch_init_deep_sx()
365 setbits_le32(RCB_REG(0x33e4), 0x1); in pch_pm_init()
372 setbits_le32(RCB_REG(0x2b1c), 1 << 29); in pch_pm_init()
383 setbits_le32(RCB_REG(0x2234), 0xf); in pch_cg_init()
406 setbits_le32(RCB_REG(0x2614), 1 << 26); in pch_cg_init()
435 setbits_le32(RCB_REG(0x3434), 0x7); in pch_cg_init()
438 setbits_le32(RCB_REG(0x38c0), 0x3c07); in pch_cg_init()
508 setbits_le32(RCB_REG(ACPIIRQEN), in serialio_init_once()
[all …]
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dlpc.c260 setbits_le32(RCB_REG(0x228c), 1 << 0); in cpt_pm_init()
270 setbits_le32(RCB_REG(0x3344), 1 << 1); in cpt_pm_init()
294 setbits_le32(RCB_REG(0x21b0), 0xf); in cpt_pm_init()
302 setbits_le32(RCB_REG(0x2238), 1 << 0); in ppt_pm_init()
303 setbits_le32(RCB_REG(0x228c), 1 << 0); in ppt_pm_init()
333 setbits_le32(RCB_REG(0x3a88), 1 << 0); in ppt_pm_init()
339 setbits_le32(RCB_REG(0x21b0), 0xf); in ppt_pm_init()
353 setbits_le32(RCB_REG(0x2234), 0xf); in enable_clock_gating()
379 setbits_le32(RCB_REG(0x38c0), 0x7); in enable_clock_gating()
381 setbits_le32(RCB_REG(0x3564), 0x3); in enable_clock_gating()
[all …]
/openbmc/u-boot/drivers/video/
H A Dbroadwell_igd.c82 setbits_le32(regs + 0xa248, 0x00000016); in haswell_early_init()
104 setbits_le32(regs + 0xa090, 0x00000000); in haswell_early_init()
105 setbits_le32(regs + 0xa098, 0x03e80000); in haswell_early_init()
106 setbits_le32(regs + 0xa09c, 0x00280000); in haswell_early_init()
107 setbits_le32(regs + 0xa0a8, 0x0001e848); in haswell_early_init()
108 setbits_le32(regs + 0xa0ac, 0x00000019); in haswell_early_init()
117 setbits_le32(regs + 0xa0b0, 0x00000000); in haswell_early_init()
118 setbits_le32(regs + 0xa0b4, 0x000003e8); in haswell_early_init()
119 setbits_le32(regs + 0xa0b8, 0x0000c350); in haswell_early_init()
169 setbits_le32(regs + 0x0a004, (1 << 4)); in haswell_late_init()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/omap3/
H A Dclock.c696 setbits_le32(&prcm_base->clksel_per, 0x000000FF); in prcm_init()
697 setbits_le32(&prcm_base->clksel_wkup, 1); in prcm_init()
710 setbits_le32(&prcm_base->iclken_usbhost, 1); in ehci_clocks_enable()
749 setbits_le32(&prcm_base->fclken_per, 0x00000800); in per_clocks_enable()
750 setbits_le32(&prcm_base->iclken_per, 0x00000800); in per_clocks_enable()
754 setbits_le32(&prcm_base->fclken_per, 0x00002000); in per_clocks_enable()
755 setbits_le32(&prcm_base->iclken_per, 0x00002000); in per_clocks_enable()
758 setbits_le32(&prcm_base->fclken_per, 0x00004000); in per_clocks_enable()
759 setbits_le32(&prcm_base->iclken_per, 0x00004000); in per_clocks_enable()
762 setbits_le32(&prcm_base->fclken_per, 0x00008000); in per_clocks_enable()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dutmi-armada100.c24 setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP); in utmi_phy_init()
26 setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP); in utmi_phy_init()
29 setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER); in utmi_phy_init()
31 setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL); in utmi_phy_init()
41 setbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
46 setbits_le32(&phy_regs->utmi_tx, RCAL_START); in utmi_phy_init()
71 setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M); in utmi_init()
H A Dehci-vf.c99 setbits_le32(usb_cmd, UCMD_RESET); in usb_phy_enable()
125 setbits_le32(ctrl, UCTRL_OVER_CUR_POL); in usb_oc_config()
126 setbits_le32(ctrl, UCTRL_OVER_CUR_DIS); in usb_oc_config()
182 setbits_le32(&ehci->usbmode, CM_DEVICE); in ehci_hcd_init()
184 setbits_le32(&ehci->portsc, USB_EN); in ehci_hcd_init()
186 setbits_le32(&ehci->usbmode, CM_HOST); in ehci_hcd_init()
188 setbits_le32(&ehci->portsc, USB_EN); in ehci_hcd_init()
282 setbits_le32(&ehci->usbmode, CM_HOST); in vf_init_after_reset()
284 setbits_le32(&ehci->portsc, USB_EN); in vf_init_after_reset()
328 setbits_le32(&ehci->usbmode, CM_HOST); in ehci_usb_probe()
[all …]
H A Dehci-omap.c99 setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI in omap_usbhs_hsic_init()
221 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); in omap_ehci_hcd_init()
226 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); in omap_ehci_hcd_init()
231 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); in omap_ehci_hcd_init()
240 setbits_le32(&reg, OMAP_P1_MODE_HSIC); in omap_ehci_hcd_init()
243 setbits_le32(&reg, OMAP_P2_MODE_HSIC); in omap_ehci_hcd_init()
256 setbits_le32(&reg, OMAP_P1_MODE_HSIC); in omap_ehci_hcd_init()
259 setbits_le32(&reg, OMAP_P2_MODE_HSIC); in omap_ehci_hcd_init()
262 setbits_le32(&reg, OMAP_P3_MODE_HSIC); in omap_ehci_hcd_init()
H A Dohci-lpc32xx.c125 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBDVND_EN); in isp1301_configure()
137 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN1); in usbpll_setup()
140 setbits_le32(&clk_pwr->usb_ctrl, in usbpll_setup()
142 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_POSTDIV_2POW(0x01)); in usbpll_setup()
143 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_PLL_PWRUP); in usbpll_setup()
151 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_CLK_EN2); in usbpll_setup()
175 setbits_le32(&clk_pwr->usb_ctrl, in usb_cpu_init()
194 setbits_le32(&clk_pwr->usb_ctrl, CLK_USBCTRL_USBHSTND_EN); in usb_cpu_init()
206 setbits_le32(&otg->otg_sts_ctrl, OTG_HOST_EN); in usb_cpu_init()
H A Dehci-exynos.c98 setbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
123 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_setup_usb_phy()
124 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_setup_usb_phy()
137 setbits_le32(&usb->ehcictrl, in exynos5_setup_usb_phy()
152 setbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); in exynos4412_setup_usb_phy()
176 setbits_le32(&usb->usbphyctrl0, in exynos5_reset_usb_phy()
189 setbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_reset_usb_phy()
190 setbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_reset_usb_phy()
195 setbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | in exynos4412_reset_usb_phy()
/openbmc/u-boot/arch/arm/mach-davinci/
H A Ddm365_lowlevel.c33 setbits_le32(&dv_pll0_regs->pllctl, in dm365_pll1_init()
48 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
97 setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
115 setbits_le32(&dv_pll1_regs->pllctl, in dm365_pll2_init()
174 setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
206 setbits_le32(&dv_sys_module_regs->vtpiocr, in dm365_ddr_setup()
247 setbits_le32(&dv_sys_module_regs->vpss_clkctl, in dm365_vpss_sync_reset()
274 setbits_le32(TMPSTATUS, FLAG_PORRST); in dm365_por_reset()
289 setbits_le32(TMPSTATUS, FLAG_PORRST); in dm365_wdt_reset()
290 setbits_le32(TMPSTATUS, FLAG_FLGOFF); in dm365_wdt_reset()
[all …]
H A Dda850_lowlevel.c61 setbits_le32(&reg->pllctl, in da850_pll_init()
69 setbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
124 setbits_le32(&reg->pllcmd, PLLCMD_GOSTAT); in da850_pll_init()
137 setbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
146 setbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
174 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
176 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
183 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); in da850_ddr_setup()
186 setbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_IOPWRDWN); in da850_ddr_setup()
196 setbits_le32(&davinci_syscfg1_regs->ddr_slew, in da850_ddr_setup()
[all …]
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dpower.c46 setbits_le32(&power->usbhost_phy_control, in exynos5_set_usbhost_phy_ctrl()
62 setbits_le32(&power->usbhost_phy_control, in exynos4412_set_usbhost_phy_ctrl()
64 setbits_le32(&power->hsic1_phy_control, in exynos4412_set_usbhost_phy_ctrl()
66 setbits_le32(&power->hsic2_phy_control, in exynos4412_set_usbhost_phy_ctrl()
95 setbits_le32(&power->usbdrd_phy_control, in exynos5_set_usbdrd_phy_ctrl()
111 setbits_le32(&power->usbdev_phy_control, in exynos5420_set_usbdev_phy_ctrl()
113 setbits_le32(&power->usbdev1_phy_control, in exynos5420_set_usbdev_phy_ctrl()
161 setbits_le32(&power->ps_hold_control, in exynos5_set_ps_hold_ctrl()
202 setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP); in set_hw_thermal_trip()
/openbmc/u-boot/drivers/fpga/
H A Dsocfpga_arria10.c47 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()
133 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cd_ratio()
232 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_reset()
283 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
293 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
316 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
341 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_init()
401 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
403 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_poll_usermode()
407 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_poll_usermode()
/openbmc/u-boot/board/sunxi/
H A Dgmac.c17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
27 setbits_le32(&ccm->gmac_clk_cfg,
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
/openbmc/u-boot/arch/arm/mach-omap2/
H A Dabb.c54 setbits_le32(setup, in abb_setup_timings()
106 setbits_le32(txdone, txdone_mask); in abb_setup()
109 setbits_le32(setup, abb_type_mask | OMAP_ABB_SETUP_SR2EN_MASK); in abb_setup()
112 setbits_le32(control, opp_sel_mask | OMAP_ABB_CONTROL_OPP_CHANGE_MASK); in abb_setup()
119 setbits_le32(txdone, txdone_mask); in abb_setup()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dspl_power_init.c71 setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq, in mxs_power_clock2pll()
104 setbits_le32(&rtc_regs->hw_rtc_persistent0, in mxs_power_set_auto_restart()
265 setbits_le32(&power_regs->hw_power_misc, in mxs_power_switch_dcdc_clocksource()
404 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
410 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
413 setbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_enable_4p2_dcdc_input()
452 setbits_le32(&power_regs->hw_power_ctrl, in mxs_enable_4p2_dcdc_input()
522 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_power_init_4p2_regulator()
743 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_batt_boot()
746 setbits_le32(&power_regs->hw_power_5vctrl, in mxs_batt_boot()
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dfreeze_controller.c129 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
138 setbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
144 setbits_le32(ioctrl_reg_offset, in sys_mgr_frzctrl_thaw_req()
160 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
190 setbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_thaw_req()
203 setbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
H A Dreset_manager_arria10.c66 setbits_le32(&reset_manager_base->per1modrst, in socfpga_watchdog_disable()
103 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc); in socfpga_reset_deassert_bridges_handoff()
150 setbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
178 setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp); in socfpga_per_reset_all()
181 setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp); in socfpga_per_reset_all()
227 setbits_le32(&reset_manager_base->brgmodrst, in socfpga_bridges_reset()
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun6i.c48 setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
159 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
190 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init()
239 setbits_le32(&mctl_ctl->dfiodtcfg, 1 << 3); in mctl_channel_init()
244 setbits_le32(&mctl_ctl->ppcfg, 1); in mctl_channel_init()
277 setbits_le32(&mctl_com->dbgcr, (1 << 6)); in mctl_com_init()
282 setbits_le32(&mctl_phy1->dxccr, MCTL_DXCCR_DISABLE); in mctl_com_init()
288 setbits_le32(&prcm->vdd_sys_pwroff, in mctl_com_init()
351 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN); in sunxi_dram_init()
355 setbits_le32(&mctl_com->ccr, MCTL_CCR_CH1_CLK_EN); in sunxi_dram_init()
[all …]
H A Ddram_sun50i_h6.c328 setbits_le32(&ccm->mbus_cfg, MBUS_RESET); in mctl_sys_init()
329 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE); in mctl_sys_init()
428 setbits_le32(&mctl_com->cr, BIT(31)); in mctl_com_init()
437 setbits_le32(&mctl_com->cr, BIT(27)); in mctl_com_init()
514 setbits_le32(&mctl_phy->pgcr[0], BIT(26)); in mctl_bit_delay_set()
538 setbits_le32(&mctl_ctl->rfshctl3, BIT(0)); in mctl_channel_init()
539 setbits_le32(&mctl_ctl->dfimisc, BIT(0)); in mctl_channel_init()
540 setbits_le32(&mctl_ctl->unk_0x00c, BIT(8)); in mctl_channel_init()
560 setbits_le32(&mctl_phy->dtcr[1], 0x30000); in mctl_channel_init()
630 setbits_le32(&mctl_phy->pgcr[6], BIT(0)); in mctl_channel_init()
[all …]
/openbmc/u-boot/drivers/usb/dwc3/
H A Dsamsung_usb_phy.c26 setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL); in exynos5_usb3_phy_init()
35 setbits_le32(&phy->link_system, in exynos5_usb3_phy_init()
41 setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH); in exynos5_usb3_phy_init()
43 setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL); in exynos5_usb3_phy_init()
/openbmc/u-boot/arch/arm/mach-omap2/omap5/
H A Dhw_data.c437 setbits_le32((*prcm)->cm_l4per_gpio4_clkctrl, in enable_basic_clocks()
441 setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl, in enable_basic_clocks()
443 setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl, in enable_basic_clocks()
453 setbits_le32((*prcm)->cm_wkup_gptimer1_clkctrl, in enable_basic_clocks()
462 setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); in enable_basic_clocks()
467 setbits_le32((*prcm)->cm_l3init_sata_clkctrl, in enable_basic_clocks()
472 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, in enable_basic_clocks()
474 setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, in enable_basic_clocks()
562 setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl, in enable_usb_clocks()
566 setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl, in enable_usb_clocks()
[all …]

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