1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
229321c05SIlya Yanok /*
329321c05SIlya Yanok * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
429321c05SIlya Yanok * (C) Copyright 2004-2008
529321c05SIlya Yanok * Texas Instruments, <www.ti.com>
629321c05SIlya Yanok *
729321c05SIlya Yanok * Derived from Beagle Board code by
829321c05SIlya Yanok * Sunil Kumar <sunilsaini05@gmail.com>
929321c05SIlya Yanok * Shashi Ranjan <shashiranjanmca05@gmail.com>
1029321c05SIlya Yanok *
1129321c05SIlya Yanok */
121a459660SWolfgang Denk
1329321c05SIlya Yanok #include <common.h>
1429321c05SIlya Yanok #include <usb.h>
1543b62393SGovindraj.R #include <usb/ulpi.h>
1643b62393SGovindraj.R #include <errno.h>
1729321c05SIlya Yanok #include <asm/io.h>
1829321c05SIlya Yanok #include <asm/gpio.h>
1943b62393SGovindraj.R #include <asm/arch/ehci.h>
2043b62393SGovindraj.R #include <asm/ehci-omap.h>
21676ae068SLucas Stach
22676ae068SLucas Stach #include "ehci.h"
2329321c05SIlya Yanok
2443b62393SGovindraj.R static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
2543b62393SGovindraj.R static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
2643b62393SGovindraj.R static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
2743b62393SGovindraj.R
omap_uhh_reset(void)2843b62393SGovindraj.R static int omap_uhh_reset(void)
2943b62393SGovindraj.R {
30835a5559SRoger Quadros int timeout = 0;
31835a5559SRoger Quadros u32 rev;
32835a5559SRoger Quadros
33835a5559SRoger Quadros rev = readl(&uhh->rev);
34835a5559SRoger Quadros
35835a5559SRoger Quadros /* Soft RESET */
36835a5559SRoger Quadros writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
37835a5559SRoger Quadros
38835a5559SRoger Quadros switch (rev) {
39835a5559SRoger Quadros case OMAP_USBHS_REV1:
40835a5559SRoger Quadros /* Wait for soft RESET to complete */
41835a5559SRoger Quadros while (!(readl(&uhh->syss) & 0x1)) {
42835a5559SRoger Quadros if (timeout > 100) {
43835a5559SRoger Quadros printf("%s: RESET timeout\n", __func__);
44835a5559SRoger Quadros return -1;
45835a5559SRoger Quadros }
46835a5559SRoger Quadros udelay(10);
47835a5559SRoger Quadros timeout++;
48835a5559SRoger Quadros }
49835a5559SRoger Quadros
50835a5559SRoger Quadros /* Set No-Idle, No-Standby */
51835a5559SRoger Quadros writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
52835a5559SRoger Quadros break;
53835a5559SRoger Quadros
54835a5559SRoger Quadros default: /* Rev. 2 onwards */
55835a5559SRoger Quadros
56835a5559SRoger Quadros udelay(2); /* Need to wait before accessing SYSCONFIG back */
57835a5559SRoger Quadros
58835a5559SRoger Quadros /* Wait for soft RESET to complete */
59835a5559SRoger Quadros while ((readl(&uhh->sysc) & 0x1)) {
60835a5559SRoger Quadros if (timeout > 100) {
61835a5559SRoger Quadros printf("%s: RESET timeout\n", __func__);
62835a5559SRoger Quadros return -1;
63835a5559SRoger Quadros }
64835a5559SRoger Quadros udelay(10);
65835a5559SRoger Quadros timeout++;
66835a5559SRoger Quadros }
67835a5559SRoger Quadros
68835a5559SRoger Quadros writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
69835a5559SRoger Quadros break;
70835a5559SRoger Quadros }
71835a5559SRoger Quadros
7243b62393SGovindraj.R return 0;
7343b62393SGovindraj.R }
7443b62393SGovindraj.R
omap_ehci_tll_reset(void)7543b62393SGovindraj.R static int omap_ehci_tll_reset(void)
7643b62393SGovindraj.R {
7743b62393SGovindraj.R unsigned long init = get_timer(0);
7843b62393SGovindraj.R
7943b62393SGovindraj.R /* perform TLL soft reset, and wait until reset is complete */
8043b62393SGovindraj.R writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
8143b62393SGovindraj.R
8243b62393SGovindraj.R /* Wait for TLL reset to complete */
8343b62393SGovindraj.R while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
8443b62393SGovindraj.R if (get_timer(init) > CONFIG_SYS_HZ) {
8543b62393SGovindraj.R debug("OMAP EHCI error: timeout resetting TLL\n");
8643b62393SGovindraj.R return -EL3RST;
8743b62393SGovindraj.R }
8843b62393SGovindraj.R
8943b62393SGovindraj.R return 0;
9043b62393SGovindraj.R }
9143b62393SGovindraj.R
omap_usbhs_hsic_init(int port)9243b62393SGovindraj.R static void omap_usbhs_hsic_init(int port)
9343b62393SGovindraj.R {
9443b62393SGovindraj.R unsigned int reg;
9543b62393SGovindraj.R
9643b62393SGovindraj.R /* Enable channels now */
9743b62393SGovindraj.R reg = readl(&usbtll->channel_conf + port);
9843b62393SGovindraj.R
9943b62393SGovindraj.R setbits_le32(®, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
10043b62393SGovindraj.R | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
10143b62393SGovindraj.R | OMAP_TLL_CHANNEL_CONF_DRVVBUS
10243b62393SGovindraj.R | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
10343b62393SGovindraj.R | OMAP_TLL_CHANNEL_CONF_CHANEN));
10443b62393SGovindraj.R
10543b62393SGovindraj.R writel(reg, &usbtll->channel_conf + port);
10643b62393SGovindraj.R }
10743b62393SGovindraj.R
108120503f3SDan Murphy #ifdef CONFIG_USB_ULPI
omap_ehci_soft_phy_reset(int port)10943b62393SGovindraj.R static void omap_ehci_soft_phy_reset(int port)
11043b62393SGovindraj.R {
11143b62393SGovindraj.R struct ulpi_viewport ulpi_vp;
11243b62393SGovindraj.R
11343b62393SGovindraj.R ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
11443b62393SGovindraj.R ulpi_vp.port_num = port;
11543b62393SGovindraj.R
11643b62393SGovindraj.R ulpi_reset(&ulpi_vp);
11743b62393SGovindraj.R }
118120503f3SDan Murphy #else
omap_ehci_soft_phy_reset(int port)119120503f3SDan Murphy static void omap_ehci_soft_phy_reset(int port)
120120503f3SDan Murphy {
121120503f3SDan Murphy return;
122120503f3SDan Murphy }
123120503f3SDan Murphy #endif
12443b62393SGovindraj.R
12529321c05SIlya Yanok #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
126d3d037aeSDan Murphy defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
127d3d037aeSDan Murphy defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
12829321c05SIlya Yanok /* controls PHY(s) reset signal(s) */
omap_ehci_phy_reset(int on,int delay)12929321c05SIlya Yanok static inline void omap_ehci_phy_reset(int on, int delay)
13029321c05SIlya Yanok {
13129321c05SIlya Yanok /*
13229321c05SIlya Yanok * Refer ISSUE1:
13329321c05SIlya Yanok * Hold the PHY in RESET for enough time till
13429321c05SIlya Yanok * PHY is settled and ready
13529321c05SIlya Yanok */
13629321c05SIlya Yanok if (delay && !on)
13729321c05SIlya Yanok udelay(delay);
13829321c05SIlya Yanok #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
13929321c05SIlya Yanok gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
14029321c05SIlya Yanok gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
14129321c05SIlya Yanok #endif
14229321c05SIlya Yanok #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
14329321c05SIlya Yanok gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
14429321c05SIlya Yanok gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
14529321c05SIlya Yanok #endif
146d3d037aeSDan Murphy #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
147d3d037aeSDan Murphy gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
148d3d037aeSDan Murphy gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
149d3d037aeSDan Murphy #endif
15029321c05SIlya Yanok
15129321c05SIlya Yanok /* Hold the PHY in RESET for enough time till DIR is high */
15229321c05SIlya Yanok /* Refer: ISSUE1 */
15329321c05SIlya Yanok if (delay && on)
15429321c05SIlya Yanok udelay(delay);
15529321c05SIlya Yanok }
15629321c05SIlya Yanok #else
15729321c05SIlya Yanok #define omap_ehci_phy_reset(on, delay) do {} while (0)
15829321c05SIlya Yanok #endif
15929321c05SIlya Yanok
16029321c05SIlya Yanok /* Reset is needed otherwise the kernel-driver will throw an error. */
omap_ehci_hcd_stop(void)16143b62393SGovindraj.R int omap_ehci_hcd_stop(void)
16229321c05SIlya Yanok {
16343b62393SGovindraj.R debug("Resetting OMAP EHCI\n");
16429321c05SIlya Yanok omap_ehci_phy_reset(1, 0);
16543b62393SGovindraj.R
16643b62393SGovindraj.R if (omap_uhh_reset() < 0)
16743b62393SGovindraj.R return -1;
16843b62393SGovindraj.R
16943b62393SGovindraj.R if (omap_ehci_tll_reset() < 0)
17043b62393SGovindraj.R return -1;
17143b62393SGovindraj.R
17229321c05SIlya Yanok return 0;
17329321c05SIlya Yanok }
17429321c05SIlya Yanok
17529321c05SIlya Yanok /*
17643b62393SGovindraj.R * Initialize the OMAP EHCI controller and PHY.
17743b62393SGovindraj.R * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
17829321c05SIlya Yanok * See there for additional Copyrights.
17929321c05SIlya Yanok */
omap_ehci_hcd_init(int index,struct omap_usbhs_board_data * usbhs_pdata,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)18016297cfbSMateusz Zalega int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
181676ae068SLucas Stach struct ehci_hccr **hccr, struct ehci_hcor **hcor)
18229321c05SIlya Yanok {
18329321c05SIlya Yanok int ret;
18443b62393SGovindraj.R unsigned int i, reg = 0, rev = 0;
18529321c05SIlya Yanok
18643b62393SGovindraj.R debug("Initializing OMAP EHCI\n");
18729321c05SIlya Yanok
18816297cfbSMateusz Zalega ret = board_usb_init(index, USB_INIT_HOST);
18929321c05SIlya Yanok if (ret < 0)
19029321c05SIlya Yanok return ret;
19129321c05SIlya Yanok
19229321c05SIlya Yanok /* Put the PHY in RESET */
19329321c05SIlya Yanok omap_ehci_phy_reset(1, 10);
19429321c05SIlya Yanok
19543b62393SGovindraj.R ret = omap_uhh_reset();
19643b62393SGovindraj.R if (ret < 0)
19743b62393SGovindraj.R return ret;
19829321c05SIlya Yanok
19943b62393SGovindraj.R ret = omap_ehci_tll_reset();
20043b62393SGovindraj.R if (ret)
20143b62393SGovindraj.R return ret;
20229321c05SIlya Yanok
20329321c05SIlya Yanok writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
20429321c05SIlya Yanok OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
20543b62393SGovindraj.R OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
20629321c05SIlya Yanok
20729321c05SIlya Yanok /* Put UHH in NoIdle/NoStandby mode */
20843b62393SGovindraj.R writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
20929321c05SIlya Yanok
21043b62393SGovindraj.R /* setup ULPI bypass and burst configurations */
21143b62393SGovindraj.R clrsetbits_le32(®, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
21243b62393SGovindraj.R (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
21343b62393SGovindraj.R OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
21443b62393SGovindraj.R OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
21543b62393SGovindraj.R
21643b62393SGovindraj.R rev = readl(&uhh->rev);
21743b62393SGovindraj.R if (rev == OMAP_USBHS_REV1) {
21843b62393SGovindraj.R if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
21943b62393SGovindraj.R clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
22043b62393SGovindraj.R else
22143b62393SGovindraj.R setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
22243b62393SGovindraj.R
22343b62393SGovindraj.R if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
22443b62393SGovindraj.R clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
22543b62393SGovindraj.R else
22690579fddSJeroen Hofstee setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
22743b62393SGovindraj.R
22843b62393SGovindraj.R if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
22943b62393SGovindraj.R clrbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
23043b62393SGovindraj.R else
23190579fddSJeroen Hofstee setbits_le32(®, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
23243b62393SGovindraj.R } else if (rev == OMAP_USBHS_REV2) {
233d3d037aeSDan Murphy
23443b62393SGovindraj.R clrsetbits_le32(®, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
23543b62393SGovindraj.R OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
23643b62393SGovindraj.R
23743b62393SGovindraj.R /* Clear port mode fields for PHY mode */
23843b62393SGovindraj.R
23943b62393SGovindraj.R if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
24043b62393SGovindraj.R setbits_le32(®, OMAP_P1_MODE_HSIC);
24143b62393SGovindraj.R
24243b62393SGovindraj.R if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
24343b62393SGovindraj.R setbits_le32(®, OMAP_P2_MODE_HSIC);
24443b62393SGovindraj.R
245d3d037aeSDan Murphy } else if (rev == OMAP_USBHS_REV2_1) {
246d3d037aeSDan Murphy
247d3d037aeSDan Murphy clrsetbits_le32(®,
248d3d037aeSDan Murphy (OMAP_P1_MODE_CLEAR |
249d3d037aeSDan Murphy OMAP_P2_MODE_CLEAR |
250d3d037aeSDan Murphy OMAP_P3_MODE_CLEAR),
251d3d037aeSDan Murphy OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
252d3d037aeSDan Murphy
253d3d037aeSDan Murphy /* Clear port mode fields for PHY mode */
254d3d037aeSDan Murphy
255d3d037aeSDan Murphy if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
256d3d037aeSDan Murphy setbits_le32(®, OMAP_P1_MODE_HSIC);
257d3d037aeSDan Murphy
258d3d037aeSDan Murphy if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
259d3d037aeSDan Murphy setbits_le32(®, OMAP_P2_MODE_HSIC);
260d3d037aeSDan Murphy
26143b62393SGovindraj.R if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
26243b62393SGovindraj.R setbits_le32(®, OMAP_P3_MODE_HSIC);
26343b62393SGovindraj.R }
26443b62393SGovindraj.R
26543b62393SGovindraj.R debug("OMAP UHH_REVISION 0x%x\n", rev);
26643b62393SGovindraj.R writel(reg, &uhh->hostconfig);
26743b62393SGovindraj.R
26843b62393SGovindraj.R for (i = 0; i < OMAP_HS_USB_PORTS; i++)
26943b62393SGovindraj.R if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
27043b62393SGovindraj.R omap_usbhs_hsic_init(i);
27129321c05SIlya Yanok
27229321c05SIlya Yanok omap_ehci_phy_reset(0, 10);
27329321c05SIlya Yanok
27443b62393SGovindraj.R /*
27543b62393SGovindraj.R * An undocumented "feature" in the OMAP3 EHCI controller,
27643b62393SGovindraj.R * causes suspended ports to be taken out of suspend when
27743b62393SGovindraj.R * the USBCMD.Run/Stop bit is cleared (for example when
27843b62393SGovindraj.R * we do ehci_bus_suspend).
27943b62393SGovindraj.R * This breaks suspend-resume if the root-hub is allowed
28043b62393SGovindraj.R * to suspend. Writing 1 to this undocumented register bit
28143b62393SGovindraj.R * disables this feature and restores normal behavior.
28243b62393SGovindraj.R */
28343b62393SGovindraj.R writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
28429321c05SIlya Yanok
28543b62393SGovindraj.R for (i = 0; i < OMAP_HS_USB_PORTS; i++)
28643b62393SGovindraj.R if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
28743b62393SGovindraj.R omap_ehci_soft_phy_reset(i);
28843b62393SGovindraj.R
289676ae068SLucas Stach *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
290676ae068SLucas Stach *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
29143b62393SGovindraj.R
29243b62393SGovindraj.R debug("OMAP EHCI init done\n");
29329321c05SIlya Yanok return 0;
29429321c05SIlya Yanok }
295