68 	setbits_le32(&phy->ctrl, BIT(0));  in sunxi_dw_hdmi_phy_init()
70 	setbits_le32(&phy->ctrl, BIT(16));  in sunxi_dw_hdmi_phy_init()
71 	setbits_le32(&phy->ctrl, BIT(1));  in sunxi_dw_hdmi_phy_init()
73 	setbits_le32(&phy->ctrl, BIT(2));  in sunxi_dw_hdmi_phy_init()
75 	setbits_le32(&phy->ctrl, BIT(3));  in sunxi_dw_hdmi_phy_init()
77 	setbits_le32(&phy->ctrl, BIT(19));  in sunxi_dw_hdmi_phy_init()
79 	setbits_le32(&phy->ctrl, BIT(18));  in sunxi_dw_hdmi_phy_init()
80 	setbits_le32(&phy->ctrl, 7 << 4);  in sunxi_dw_hdmi_phy_init()
91 	setbits_le32(&phy->ctrl, 0xf << 8);  in sunxi_dw_hdmi_phy_init()
92 	setbits_le32(&phy->ctrl, BIT(7));  in sunxi_dw_hdmi_phy_init()
98 	setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_init()
101 	setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_init()
102 	setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_init()
152 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
155 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
157 			setbits_le32(&phy->pll, tmp + 2);  in sunxi_dw_hdmi_phy_set()
159 			setbits_le32(&phy->pll, 0x3f);  in sunxi_dw_hdmi_phy_set()
170 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
173 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
174 		setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_set()
184 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
187 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
188 		setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_set()
198 		setbits_le32(&phy->pll, BIT(25));  in sunxi_dw_hdmi_phy_set()
201 		setbits_le32(&phy->pll, BIT(31) | BIT(30));  in sunxi_dw_hdmi_phy_set()
202 		setbits_le32(&phy->pll, tmp);  in sunxi_dw_hdmi_phy_set()
264 		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD0);  in sunxi_dw_hdmi_lcdc_init()
267 		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD0);  in sunxi_dw_hdmi_lcdc_init()
274 		setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_LCD1);  in sunxi_dw_hdmi_lcdc_init()
277 		setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_LCD1);  in sunxi_dw_hdmi_lcdc_init()
319 		setbits_le32(&phy->pol, 0x200);  in sunxi_dw_hdmi_enable()
322 		setbits_le32(&phy->pol, 0x100);  in sunxi_dw_hdmi_enable()
324 	setbits_le32(&phy->ctrl, 0xf << 12);  in sunxi_dw_hdmi_enable()
353 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI);  in sunxi_dw_hdmi_probe()
354 	setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_HDMI2);  in sunxi_dw_hdmi_probe()
355 	setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_HDMI);  in sunxi_dw_hdmi_probe()
356 	setbits_le32(&ccm->hdmi_slow_clk_cfg, CCM_HDMI_SLOW_CTRL_DDC_GATE);  in sunxi_dw_hdmi_probe()
359 	setbits_le32(&ccm->hdmi_clk_cfg, CCM_HDMI_CTRL_GATE);  in sunxi_dw_hdmi_probe()