60 	setbits_le32(HPET_BASE_ADDRESS + 0x10, 1 << 0);  in broadwell_pch_early_init()
62 	setbits_le32(RCB_REG(GCS), 1 << 5);  in broadwell_pch_early_init()
100 	setbits_le32(RCB_REG(0x3310), 0x0000002f);  in pch_misc_init()
103 	setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7);  in pch_misc_init()
104 	setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14);  in pch_misc_init()
212 	setbits_le32(RCB_REG(0x1100), 0x0000c13f);  in pch_pm_init_magic()
242 	setbits_le32(RCB_REG(0x0410), 0x00000003);  in pch_pm_init_magic()
243 	setbits_le32(RCB_REG(0x2618), 0x08000000);  in pch_pm_init_magic()
244 	setbits_le32(RCB_REG(0x2300), 0x00000002);  in pch_pm_init_magic()
245 	setbits_le32(RCB_REG(0x2600), 0x00000008);  in pch_pm_init_magic()
250 	setbits_le32(RCB_REG(0x33d4), 0x08000000);  in pch_pm_init_magic()
261 	setbits_le32(RCB_REG(0x33d4), 0x2fff2fb1);  in pch_pm_init_magic()
262 	setbits_le32(RCB_REG(0x33c8), 0x00008000);  in pch_pm_init_magic()
298 	setbits_le32(SPI_REG(SPIBAR_FDOC), 0x00004000 | id * 4);  in pch_read_soft_strap()
337 		setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_AC);  in pch_init_deep_sx()
338 		setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_AC);  in pch_init_deep_sx()
342 		setbits_le32(RCB_REG(DEEP_S3_POL), DEEP_S3_EN_DC);  in pch_init_deep_sx()
343 		setbits_le32(RCB_REG(DEEP_S5_POL), DEEP_S5_EN_DC);  in pch_init_deep_sx()
347 		setbits_le32(RCB_REG(DEEP_SX_CONFIG),  in pch_init_deep_sx()
362 		setbits_le32(RCB_REG(0x33e0), 1 << 4 | 1 << 1);  in pch_pm_init()
363 		setbits_le32(RCB_REG(0x2b1c), 1 << 22 | 1 << 14 | 1 << 13);  in pch_pm_init()
365 		setbits_le32(RCB_REG(0x33e4), 0x1);  in pch_pm_init()
372 		setbits_le32(RCB_REG(0x2b1c), 1 << 29);  in pch_pm_init()
383 	setbits_le32(RCB_REG(0x2234), 0xf);  in pch_cg_init()
406 		setbits_le32(RCB_REG(0x2614), 1 << 26);  in pch_cg_init()
408 	setbits_le32(RCB_REG(0x900), 0x0000031f);  in pch_cg_init()
435 		setbits_le32(RCB_REG(0x3434), 0x7);  in pch_cg_init()
438 	setbits_le32(RCB_REG(0x38c0), 0x3c07);  in pch_cg_init()
471 	setbits_le32(bar0 + SIO_REG_PPR_RST, SIO_REG_PPR_RST_ASSERT);  in serialio_d21_ltr()
508 		setbits_le32(RCB_REG(ACPIIRQEN),  in serialio_init_once()
547 	setbits_le32(bar1 + PCH_PCS, PCH_PCS_PS_D3HOT);  in pch_serialio_init()
551 	setbits_le32(bar0 + SIO_REG_PPR_CLOCK, SIO_REG_PPR_CLOCK_EN);  in pch_serialio_init()
571 	setbits_le32(RCB_REG(RC), 1 << 2);  in broadwell_pch_init()
579 	setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);  in broadwell_pch_init()