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Searched refs:reg_shift (Results 1 – 25 of 25) sorted by relevance

/openbmc/u-boot/drivers/i2c/
H A Dmxc_i2c.c175 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; in bus_i2c_set_bus_speed() local
181 writeb(idx, base + (IFDR << reg_shift)); in bus_i2c_set_bus_speed()
184 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); in bus_i2c_set_bus_speed()
185 writeb(0, base + (I2SR << reg_shift)); in bus_i2c_set_bus_speed()
198 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; in wait_for_sr_state() local
202 sr = readb(base + (I2SR << reg_shift)); in wait_for_sr_state()
206 (I2SR << reg_shift)); in wait_for_sr_state()
209 (I2SR << reg_shift)); in wait_for_sr_state()
211 __func__, sr, readb(base + (I2CR << reg_shift)), in wait_for_sr_state()
223 sr, readb(base + (I2CR << reg_shift)), state); in wait_for_sr_state()
[all …]
/openbmc/u-boot/drivers/net/
H A Ddwmac_socfpga.c23 u32 reg_shift; member
60 pdata->reg_shift = args.args[1]; in dwmac_socfpga_ofdata_to_platdata()
98 modemask = SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << pdata->reg_shift; in dwmac_socfpga_probe()
100 modereg << pdata->reg_shift); in dwmac_socfpga_probe()
/openbmc/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddevices.c47 { .base = UART3_BASE, .reg_shift = 2,
49 { .base = UART4_BASE, .reg_shift = 2,
51 { .base = UART5_BASE, .reg_shift = 2,
53 { .base = UART6_BASE, .reg_shift = 2,
/openbmc/qemu/target/arm/tcg/
H A Dneon-dp.decode189 &2reg_shift vm vd q shift size
198 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 shift=%neon_rshift_i6
200 &2reg_shift vm=%vm_dp vd=%vd_dp size=2 shift=%neon_rshift_i5
202 &2reg_shift vm=%vm_dp vd=%vd_dp size=1 shift=%neon_rshift_i4
204 &2reg_shift vm=%vm_dp vd=%vd_dp size=0 shift=%neon_rshift_i3
207 &2reg_shift vm=%vm_dp vd=%vd_dp size=3
209 &2reg_shift vm=%vm_dp vd=%vd_dp size=2
211 &2reg_shift vm=%vm_dp vd=%vd_dp size=1
213 &2reg_shift vm=%vm_dp vd=%vd_dp size=0
217 &2reg_shift vm=%vm_dp vd=%vd_dp size=3 q=0 \
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dboard.c66 { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
69 { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
72 { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
74 { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
76 { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
78 { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
/openbmc/u-boot/drivers/serial/
H A Dserial_rockchip.c34 plat->plat.reg_shift = plat->dtplat.reg_shift; in rockchip_serial_probe()
H A Dns16550.c100 offset *= 1 << plat->reg_shift; in ns16550_writeb()
107 serial_out_shift(addr + plat->reg_offset, plat->reg_shift, value); in ns16550_writeb()
115 offset *= 1 << plat->reg_shift; in ns16550_readb()
118 return serial_in_shift(addr + plat->reg_offset, plat->reg_shift); in ns16550_readb()
405 info->reg_shift = plat->reg_shift; in ns16550_serial_getinfo()
483 plat->reg_shift = dev_read_u32_default(dev, "reg-shift", 0); in ns16550_serial_ofdata_to_platdata()
H A Dserial_intel_mid.c28 offset *= 1 << plat->reg_shift; in mid_writel()
H A Dserial_omap.c115 plat->reg_shift = 2; in omap_serial_ofdata_to_platdata()
H A Dsandbox.c200 .reg_shift = 0, in sandbox_serial_getinfo()
/openbmc/u-boot/drivers/gpio/
H A Dhsdk-creg-gpio.c32 u8 reg_shift = oft * hcg->bit_per_gpio + hcg->shift; in hsdk_creg_gpio_set_value() local
35 reg &= ~(GENMASK(hcg->bit_per_gpio - 1, 0) << reg_shift); in hsdk_creg_gpio_set_value()
36 reg |= ((val ? hcg->deactivate : hcg->activate) << reg_shift); in hsdk_creg_gpio_set_value()
/openbmc/u-boot/board/quipos/cairo/
H A Dcairo.c82 .reg_shift = 2,
/openbmc/u-boot/board/logicpd/zoom1/
H A Dzoom1.c49 .reg_shift = 2,
/openbmc/u-boot/board/pandora/
H A Dpandora.c40 .reg_shift = 2,
/openbmc/u-boot/board/timll/devkit8000/
H A Ddevkit8000.c50 .reg_shift = 2,
/openbmc/u-boot/board/lg/sniper/
H A Dsniper.c32 .reg_shift = 2,
/openbmc/u-boot/include/
H A Dns16550.h59 int reg_shift; member
H A Dserial.h148 u8 reg_shift; member
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dboard.c219 .reg_shift = 2,
/openbmc/u-boot/board/isee/igep00x0/
H A Digep00x0.c29 .reg_shift = 2,
/openbmc/u-boot/board/overo/
H A Dovero.c69 .reg_shift = 2,
/openbmc/u-boot/arch/x86/lib/
H A Dacpi_table.c387 serial_offset = serial_info.reg_offset << serial_info.reg_shift; in acpi_create_spcr()
391 switch (serial_info.reg_shift) { in acpi_create_spcr()
/openbmc/u-boot/board/davinci/da8xxevm/
H A Dda850evm.c58 .reg_shift = 2,
/openbmc/qemu/hw/char/
H A Descc.c200 static int reg_shift(ESCCState *s) in reg_shift() function
547 saddr = (addr >> reg_shift(serial)) & 1; in escc_mem_write()
687 saddr = (addr >> reg_shift(serial)) & 1; in escc_mem_read()
/openbmc/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c922 unsigned int reg_shift[DP_LANE_CNT_4] = { in exynos_dp_set_lane_pre_emphasis() local
930 reg = level << reg_shift[i]; in exynos_dp_set_lane_pre_emphasis()