1717b5aadSwdenk /* 2717b5aadSwdenk * NS16550 Serial Port 3a47a12beSStefan Roese * originally from linux source (arch/powerpc/boot/ns16550.h) 4200779e3SDetlev Zundel * 5200779e3SDetlev Zundel * Cleanup and unification 6200779e3SDetlev Zundel * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH 7200779e3SDetlev Zundel * 8717b5aadSwdenk * modified slightly to 96d0f6bcfSJean-Christophe PLAGNIOL-VILLARD * have addresses as offsets from CONFIG_SYS_ISA_BASE 10717b5aadSwdenk * added a few more definitions 11717b5aadSwdenk * added prototypes for ns16550.c 12717b5aadSwdenk * reduced no of com ports to 2 13717b5aadSwdenk * modifications (c) Rob Taylor, Flying Pig Systems. 2000. 14f5e0d039SHeiko Schocher * 15f5e0d039SHeiko Schocher * added support for port on 64-bit bus 16f5e0d039SHeiko Schocher * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems 17717b5aadSwdenk */ 18717b5aadSwdenk 19453c0d75SDetlev Zundel /* 20453c0d75SDetlev Zundel * Note that the following macro magic uses the fact that the compiler 21453c0d75SDetlev Zundel * will not allocate storage for arrays of size 0 22453c0d75SDetlev Zundel */ 23453c0d75SDetlev Zundel 2479df1208SDave Aldridge #include <linux/types.h> 2579df1208SDave Aldridge 2612e431b2SSimon Glass #ifdef CONFIG_DM_SERIAL 2712e431b2SSimon Glass /* 2812e431b2SSimon Glass * For driver model we always use one byte per register, and sort out the 2912e431b2SSimon Glass * differences in the driver 3012e431b2SSimon Glass */ 3112e431b2SSimon Glass #define CONFIG_SYS_NS16550_REG_SIZE (-1) 3212e431b2SSimon Glass #endif 3312e431b2SSimon Glass 34453c0d75SDetlev Zundel #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) 35717b5aadSwdenk #error "Please define NS16550 registers size." 3690914008SSimon Glass #elif defined(CONFIG_SYS_NS16550_MEM32) && !defined(CONFIG_DM_SERIAL) 3779df1208SDave Aldridge #define UART_REG(x) u32 x 38453c0d75SDetlev Zundel #elif (CONFIG_SYS_NS16550_REG_SIZE > 0) 39453c0d75SDetlev Zundel #define UART_REG(x) \ 40453c0d75SDetlev Zundel unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ 41453c0d75SDetlev Zundel unsigned char x; 42453c0d75SDetlev Zundel #elif (CONFIG_SYS_NS16550_REG_SIZE < 0) 43453c0d75SDetlev Zundel #define UART_REG(x) \ 44453c0d75SDetlev Zundel unsigned char x; \ 45453c0d75SDetlev Zundel unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; 46717b5aadSwdenk #endif 47717b5aadSwdenk 4812e431b2SSimon Glass /** 4912e431b2SSimon Glass * struct ns16550_platdata - information about a NS16550 port 5012e431b2SSimon Glass * 5112e431b2SSimon Glass * @base: Base register address 52*4e720779SAndy Shevchenko * @reg_width: IO accesses size of registers (in bytes) 5312e431b2SSimon Glass * @reg_shift: Shift size of registers (0=byte, 1=16bit, 2=32bit...) 5412e431b2SSimon Glass * @clock: UART base clock speed in Hz 5512e431b2SSimon Glass */ 5612e431b2SSimon Glass struct ns16550_platdata { 57167efe01SSimon Glass unsigned long base; 58*4e720779SAndy Shevchenko int reg_width; 5912e431b2SSimon Glass int reg_shift; 6059b35dddSMichal Simek int reg_offset; 610af76162SAndy Shevchenko int clock; 6265f83802SMarek Vasut u32 fcr; 6312e431b2SSimon Glass }; 6412e431b2SSimon Glass 6512e431b2SSimon Glass struct udevice; 6612e431b2SSimon Glass 67453c0d75SDetlev Zundel struct NS16550 { 68453c0d75SDetlev Zundel UART_REG(rbr); /* 0 */ 69453c0d75SDetlev Zundel UART_REG(ier); /* 1 */ 70453c0d75SDetlev Zundel UART_REG(fcr); /* 2 */ 71453c0d75SDetlev Zundel UART_REG(lcr); /* 3 */ 72453c0d75SDetlev Zundel UART_REG(mcr); /* 4 */ 73453c0d75SDetlev Zundel UART_REG(lsr); /* 5 */ 74453c0d75SDetlev Zundel UART_REG(msr); /* 6 */ 75453c0d75SDetlev Zundel UART_REG(spr); /* 7 */ 7699b603e7SMikhail Kshevetskiy #ifdef CONFIG_SOC_DA8XX 7799b603e7SMikhail Kshevetskiy UART_REG(reg8); /* 8 */ 7899b603e7SMikhail Kshevetskiy UART_REG(reg9); /* 9 */ 7999b603e7SMikhail Kshevetskiy UART_REG(revid1); /* A */ 8099b603e7SMikhail Kshevetskiy UART_REG(revid2); /* B */ 8199b603e7SMikhail Kshevetskiy UART_REG(pwr_mgmt); /* C */ 8299b603e7SMikhail Kshevetskiy UART_REG(mdr1); /* D */ 8399b603e7SMikhail Kshevetskiy #else 84453c0d75SDetlev Zundel UART_REG(mdr1); /* 8 */ 85453c0d75SDetlev Zundel UART_REG(reg9); /* 9 */ 86453c0d75SDetlev Zundel UART_REG(regA); /* A */ 87453c0d75SDetlev Zundel UART_REG(regB); /* B */ 88453c0d75SDetlev Zundel UART_REG(regC); /* C */ 89453c0d75SDetlev Zundel UART_REG(regD); /* D */ 90453c0d75SDetlev Zundel UART_REG(regE); /* E */ 91453c0d75SDetlev Zundel UART_REG(uasr); /* F */ 92453c0d75SDetlev Zundel UART_REG(scr); /* 10*/ 93453c0d75SDetlev Zundel UART_REG(ssr); /* 11*/ 9499b603e7SMikhail Kshevetskiy #endif 9512e431b2SSimon Glass #ifdef CONFIG_DM_SERIAL 9612e431b2SSimon Glass struct ns16550_platdata *plat; 9712e431b2SSimon Glass #endif 98453c0d75SDetlev Zundel }; 99453c0d75SDetlev Zundel 100717b5aadSwdenk #define thr rbr 101717b5aadSwdenk #define iir fcr 102717b5aadSwdenk #define dll rbr 103717b5aadSwdenk #define dlm ier 104717b5aadSwdenk 105f8df9d0dSSimon Glass typedef struct NS16550 *NS16550_t; 106717b5aadSwdenk 107200779e3SDetlev Zundel /* 108200779e3SDetlev Zundel * These are the definitions for the FIFO Control Register 109200779e3SDetlev Zundel */ 110200779e3SDetlev Zundel #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */ 111200779e3SDetlev Zundel #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 112200779e3SDetlev Zundel #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 113200779e3SDetlev Zundel #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 114200779e3SDetlev Zundel #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 115200779e3SDetlev Zundel #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 116200779e3SDetlev Zundel #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 117200779e3SDetlev Zundel #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 118200779e3SDetlev Zundel #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 119717b5aadSwdenk 120200779e3SDetlev Zundel #define UART_FCR_RXSR 0x02 /* Receiver soft reset */ 121200779e3SDetlev Zundel #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */ 122717b5aadSwdenk 1230b060eefSMarek Vasut /* Ingenic JZ47xx specific UART-enable bit. */ 1240b060eefSMarek Vasut #define UART_FCR_UME 0x10 1250b060eefSMarek Vasut 12617fa0326SHeiko Schocher /* Clear & enable FIFOs */ 12717fa0326SHeiko Schocher #define UART_FCR_DEFVAL (UART_FCR_FIFO_EN | \ 12817fa0326SHeiko Schocher UART_FCR_RXSR | \ 12917fa0326SHeiko Schocher UART_FCR_TXSR) 13017fa0326SHeiko Schocher 131200779e3SDetlev Zundel /* 132200779e3SDetlev Zundel * These are the definitions for the Modem Control Register 133200779e3SDetlev Zundel */ 134200779e3SDetlev Zundel #define UART_MCR_DTR 0x01 /* DTR */ 135200779e3SDetlev Zundel #define UART_MCR_RTS 0x02 /* RTS */ 136200779e3SDetlev Zundel #define UART_MCR_OUT1 0x04 /* Out 1 */ 137200779e3SDetlev Zundel #define UART_MCR_OUT2 0x08 /* Out 2 */ 138200779e3SDetlev Zundel #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 139d57dee57SKaricheri, Muralidharan #define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS */ 140717b5aadSwdenk 141200779e3SDetlev Zundel #define UART_MCR_DMA_EN 0x04 142200779e3SDetlev Zundel #define UART_MCR_TX_DFR 0x08 143717b5aadSwdenk 144200779e3SDetlev Zundel /* 145200779e3SDetlev Zundel * These are the definitions for the Line Control Register 146200779e3SDetlev Zundel * 147200779e3SDetlev Zundel * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 148200779e3SDetlev Zundel * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 149200779e3SDetlev Zundel */ 150200779e3SDetlev Zundel #define UART_LCR_WLS_MSK 0x03 /* character length select mask */ 151200779e3SDetlev Zundel #define UART_LCR_WLS_5 0x00 /* 5 bit character length */ 152200779e3SDetlev Zundel #define UART_LCR_WLS_6 0x01 /* 6 bit character length */ 153200779e3SDetlev Zundel #define UART_LCR_WLS_7 0x02 /* 7 bit character length */ 154200779e3SDetlev Zundel #define UART_LCR_WLS_8 0x03 /* 8 bit character length */ 155f8df9d0dSSimon Glass #define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */ 156200779e3SDetlev Zundel #define UART_LCR_PEN 0x08 /* Parity eneble */ 157200779e3SDetlev Zundel #define UART_LCR_EPS 0x10 /* Even Parity Select */ 158200779e3SDetlev Zundel #define UART_LCR_STKP 0x20 /* Stick Parity */ 159200779e3SDetlev Zundel #define UART_LCR_SBRK 0x40 /* Set Break */ 160200779e3SDetlev Zundel #define UART_LCR_BKSE 0x80 /* Bank select enable */ 161200779e3SDetlev Zundel #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 162200779e3SDetlev Zundel 163200779e3SDetlev Zundel /* 164200779e3SDetlev Zundel * These are the definitions for the Line Status Register 165200779e3SDetlev Zundel */ 166200779e3SDetlev Zundel #define UART_LSR_DR 0x01 /* Data ready */ 167200779e3SDetlev Zundel #define UART_LSR_OE 0x02 /* Overrun */ 168200779e3SDetlev Zundel #define UART_LSR_PE 0x04 /* Parity error */ 169200779e3SDetlev Zundel #define UART_LSR_FE 0x08 /* Framing error */ 170200779e3SDetlev Zundel #define UART_LSR_BI 0x10 /* Break */ 171200779e3SDetlev Zundel #define UART_LSR_THRE 0x20 /* Xmit holding register empty */ 172200779e3SDetlev Zundel #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 173200779e3SDetlev Zundel #define UART_LSR_ERR 0x80 /* Error */ 174200779e3SDetlev Zundel 175200779e3SDetlev Zundel #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 176200779e3SDetlev Zundel #define UART_MSR_RI 0x40 /* Ring Indicator */ 177200779e3SDetlev Zundel #define UART_MSR_DSR 0x20 /* Data Set Ready */ 178200779e3SDetlev Zundel #define UART_MSR_CTS 0x10 /* Clear to Send */ 179200779e3SDetlev Zundel #define UART_MSR_DDCD 0x08 /* Delta DCD */ 180200779e3SDetlev Zundel #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 181200779e3SDetlev Zundel #define UART_MSR_DDSR 0x02 /* Delta DSR */ 182200779e3SDetlev Zundel #define UART_MSR_DCTS 0x01 /* Delta CTS */ 183200779e3SDetlev Zundel 184200779e3SDetlev Zundel /* 185200779e3SDetlev Zundel * These are the definitions for the Interrupt Identification Register 186200779e3SDetlev Zundel */ 187200779e3SDetlev Zundel #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 188200779e3SDetlev Zundel #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 189200779e3SDetlev Zundel 190200779e3SDetlev Zundel #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 191200779e3SDetlev Zundel #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 192200779e3SDetlev Zundel #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 193200779e3SDetlev Zundel #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 194200779e3SDetlev Zundel 195200779e3SDetlev Zundel /* 196200779e3SDetlev Zundel * These are the definitions for the Interrupt Enable Register 197200779e3SDetlev Zundel */ 198200779e3SDetlev Zundel #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 199200779e3SDetlev Zundel #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 200200779e3SDetlev Zundel #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 201200779e3SDetlev Zundel #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 202200779e3SDetlev Zundel 203717b5aadSwdenk /* useful defaults for LCR */ 204200779e3SDetlev Zundel #define UART_LCR_8N1 0x03 205717b5aadSwdenk 206717b5aadSwdenk void NS16550_init(NS16550_t com_port, int baud_divisor); 207717b5aadSwdenk void NS16550_putc(NS16550_t com_port, char c); 208717b5aadSwdenk char NS16550_getc(NS16550_t com_port); 209717b5aadSwdenk int NS16550_tstc(NS16550_t com_port); 210717b5aadSwdenk void NS16550_reinit(NS16550_t com_port, int baud_divisor); 211fa54eb12SSimon Glass 212fa54eb12SSimon Glass /** 213fa54eb12SSimon Glass * ns16550_calc_divisor() - calculate the divisor given clock and baud rate 214fa54eb12SSimon Glass * 215fa54eb12SSimon Glass * Given the UART input clock and required baudrate, calculate the divisor 216fa54eb12SSimon Glass * that should be used. 217fa54eb12SSimon Glass * 218fa54eb12SSimon Glass * @port: UART port 219fa54eb12SSimon Glass * @clock: UART input clock speed in Hz 220fa54eb12SSimon Glass * @baudrate: Required baud rate 221fa54eb12SSimon Glass * @return baud rate divisor that should be used 222fa54eb12SSimon Glass */ 223fa54eb12SSimon Glass int ns16550_calc_divisor(NS16550_t port, int clock, int baudrate); 22412e431b2SSimon Glass 22512e431b2SSimon Glass /** 22612e431b2SSimon Glass * ns16550_serial_ofdata_to_platdata() - convert DT to platform data 22712e431b2SSimon Glass * 22812e431b2SSimon Glass * Decode a device tree node for an ns16550 device. This includes the 22912e431b2SSimon Glass * register base address and register shift properties. The caller must set 23012e431b2SSimon Glass * up the clock frequency. 23112e431b2SSimon Glass * 23212e431b2SSimon Glass * @dev: dev to decode platform data for 23312e431b2SSimon Glass * @return: 0 if OK, -EINVAL on error 23412e431b2SSimon Glass */ 23512e431b2SSimon Glass int ns16550_serial_ofdata_to_platdata(struct udevice *dev); 23612e431b2SSimon Glass 23712e431b2SSimon Glass /** 23812e431b2SSimon Glass * ns16550_serial_probe() - probe a serial port 23912e431b2SSimon Glass * 24012e431b2SSimon Glass * This sets up the serial port ready for use, except for the baud rate 24112e431b2SSimon Glass * @return 0, or -ve on error 24212e431b2SSimon Glass */ 24312e431b2SSimon Glass int ns16550_serial_probe(struct udevice *dev); 24412e431b2SSimon Glass 24512e431b2SSimon Glass /** 24612e431b2SSimon Glass * struct ns16550_serial_ops - ns16550 serial operations 24712e431b2SSimon Glass * 24812e431b2SSimon Glass * These should be used by the client driver for the driver's 'ops' member 24912e431b2SSimon Glass */ 25012e431b2SSimon Glass extern const struct dm_serial_ops ns16550_serial_ops; 251