183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2983e3700STom Rini /*
3983e3700STom Rini * board.c
4983e3700STom Rini *
5983e3700STom Rini * Common board functions for AM33XX based boards
6983e3700STom Rini *
7983e3700STom Rini * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8983e3700STom Rini */
9983e3700STom Rini
10983e3700STom Rini #include <common.h>
11983e3700STom Rini #include <dm.h>
12878d8856SLokesh Vutla #include <debug_uart.h>
13983e3700STom Rini #include <errno.h>
14983e3700STom Rini #include <ns16550.h>
15983e3700STom Rini #include <spl.h>
16983e3700STom Rini #include <asm/arch/cpu.h>
17983e3700STom Rini #include <asm/arch/hardware.h>
18983e3700STom Rini #include <asm/arch/omap.h>
19983e3700STom Rini #include <asm/arch/ddr_defs.h>
20983e3700STom Rini #include <asm/arch/clock.h>
21983e3700STom Rini #include <asm/arch/gpio.h>
220e6e67c6SJean-Jacques Hiblot #include <asm/arch/i2c.h>
23983e3700STom Rini #include <asm/arch/mem.h>
24983e3700STom Rini #include <asm/arch/mmc_host_def.h>
25983e3700STom Rini #include <asm/arch/sys_proto.h>
26983e3700STom Rini #include <asm/io.h>
27983e3700STom Rini #include <asm/emif.h>
28983e3700STom Rini #include <asm/gpio.h>
2900bbe96eSSemen Protsenko #include <asm/omap_common.h>
30983e3700STom Rini #include <i2c.h>
31983e3700STom Rini #include <miiphy.h>
32983e3700STom Rini #include <cpsw.h>
33983e3700STom Rini #include <linux/errno.h>
34983e3700STom Rini #include <linux/compiler.h>
35983e3700STom Rini #include <linux/usb/ch9.h>
36983e3700STom Rini #include <linux/usb/gadget.h>
37983e3700STom Rini #include <linux/usb/musb.h>
38983e3700STom Rini #include <asm/omap_musb.h>
39983e3700STom Rini #include <asm/davinci_rtc.h>
40983e3700STom Rini
41983e3700STom Rini DECLARE_GLOBAL_DATA_PTR;
42983e3700STom Rini
dram_init(void)4386277339STom Rini int dram_init(void)
4486277339STom Rini {
4586277339STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT
4686277339STom Rini sdram_init();
4786277339STom Rini #endif
4886277339STom Rini
4986277339STom Rini /* dram_init must store complete ramsize in gd->ram_size */
5086277339STom Rini gd->ram_size = get_ram_size(
5186277339STom Rini (void *)CONFIG_SYS_SDRAM_BASE,
5286277339STom Rini CONFIG_MAX_RAM_BANK_SIZE);
5386277339STom Rini return 0;
5486277339STom Rini }
5586277339STom Rini
dram_init_banksize(void)5686277339STom Rini int dram_init_banksize(void)
5786277339STom Rini {
5886277339STom Rini gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
5986277339STom Rini gd->bd->bi_dram[0].size = gd->ram_size;
6086277339STom Rini
6186277339STom Rini return 0;
6286277339STom Rini }
6386277339STom Rini
64983e3700STom Rini #if !CONFIG_IS_ENABLED(OF_CONTROL)
65983e3700STom Rini static const struct ns16550_platdata am33xx_serial[] = {
6617fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
6717fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
68983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2
6917fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM2, .reg_shift = 2,
7017fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
71983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3
7217fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM3, .reg_shift = 2,
7317fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
7417fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM4, .reg_shift = 2,
7517fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
7617fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM5, .reg_shift = 2,
7717fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
7817fa0326SHeiko Schocher { .base = CONFIG_SYS_NS16550_COM6, .reg_shift = 2,
7917fa0326SHeiko Schocher .clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
80983e3700STom Rini # endif
81983e3700STom Rini # endif
82983e3700STom Rini };
83983e3700STom Rini
84983e3700STom Rini U_BOOT_DEVICES(am33xx_uarts) = {
85983e3700STom Rini { "ns16550_serial", &am33xx_serial[0] },
86983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM2
87983e3700STom Rini { "ns16550_serial", &am33xx_serial[1] },
88983e3700STom Rini # ifdef CONFIG_SYS_NS16550_COM3
89983e3700STom Rini { "ns16550_serial", &am33xx_serial[2] },
90983e3700STom Rini { "ns16550_serial", &am33xx_serial[3] },
91983e3700STom Rini { "ns16550_serial", &am33xx_serial[4] },
92983e3700STom Rini { "ns16550_serial", &am33xx_serial[5] },
93983e3700STom Rini # endif
94983e3700STom Rini # endif
95983e3700STom Rini };
96983e3700STom Rini
970e6e67c6SJean-Jacques Hiblot #ifdef CONFIG_DM_I2C
980e6e67c6SJean-Jacques Hiblot static const struct omap_i2c_platdata am33xx_i2c[] = {
990e6e67c6SJean-Jacques Hiblot { I2C_BASE1, 100000, OMAP_I2C_REV_V2},
1000e6e67c6SJean-Jacques Hiblot { I2C_BASE2, 100000, OMAP_I2C_REV_V2},
1010e6e67c6SJean-Jacques Hiblot { I2C_BASE3, 100000, OMAP_I2C_REV_V2},
1020e6e67c6SJean-Jacques Hiblot };
1030e6e67c6SJean-Jacques Hiblot
1040e6e67c6SJean-Jacques Hiblot U_BOOT_DEVICES(am33xx_i2c) = {
1050e6e67c6SJean-Jacques Hiblot { "i2c_omap", &am33xx_i2c[0] },
1060e6e67c6SJean-Jacques Hiblot { "i2c_omap", &am33xx_i2c[1] },
1070e6e67c6SJean-Jacques Hiblot { "i2c_omap", &am33xx_i2c[2] },
1080e6e67c6SJean-Jacques Hiblot };
1090e6e67c6SJean-Jacques Hiblot #endif
1100e6e67c6SJean-Jacques Hiblot
111983e3700STom Rini #ifdef CONFIG_DM_GPIO
112983e3700STom Rini static const struct omap_gpio_platdata am33xx_gpio[] = {
113983e3700STom Rini { 0, AM33XX_GPIO0_BASE },
114983e3700STom Rini { 1, AM33XX_GPIO1_BASE },
115983e3700STom Rini { 2, AM33XX_GPIO2_BASE },
116983e3700STom Rini { 3, AM33XX_GPIO3_BASE },
117983e3700STom Rini #ifdef CONFIG_AM43XX
118983e3700STom Rini { 4, AM33XX_GPIO4_BASE },
119983e3700STom Rini { 5, AM33XX_GPIO5_BASE },
120983e3700STom Rini #endif
121983e3700STom Rini };
122983e3700STom Rini
123983e3700STom Rini U_BOOT_DEVICES(am33xx_gpios) = {
124983e3700STom Rini { "gpio_omap", &am33xx_gpio[0] },
125983e3700STom Rini { "gpio_omap", &am33xx_gpio[1] },
126983e3700STom Rini { "gpio_omap", &am33xx_gpio[2] },
127983e3700STom Rini { "gpio_omap", &am33xx_gpio[3] },
128983e3700STom Rini #ifdef CONFIG_AM43XX
129983e3700STom Rini { "gpio_omap", &am33xx_gpio[4] },
130983e3700STom Rini { "gpio_omap", &am33xx_gpio[5] },
131983e3700STom Rini #endif
132983e3700STom Rini };
133983e3700STom Rini #endif
134983e3700STom Rini #endif
135983e3700STom Rini
136983e3700STom Rini #ifndef CONFIG_DM_GPIO
137983e3700STom Rini static const struct gpio_bank gpio_bank_am33xx[] = {
138983e3700STom Rini { (void *)AM33XX_GPIO0_BASE },
139983e3700STom Rini { (void *)AM33XX_GPIO1_BASE },
140983e3700STom Rini { (void *)AM33XX_GPIO2_BASE },
141983e3700STom Rini { (void *)AM33XX_GPIO3_BASE },
142983e3700STom Rini #ifdef CONFIG_AM43XX
143983e3700STom Rini { (void *)AM33XX_GPIO4_BASE },
144983e3700STom Rini { (void *)AM33XX_GPIO5_BASE },
145983e3700STom Rini #endif
146983e3700STom Rini };
147983e3700STom Rini
148983e3700STom Rini const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
149983e3700STom Rini #endif
150983e3700STom Rini
151d5abcf94SJean-Jacques Hiblot #if defined(CONFIG_MMC_OMAP_HS)
cpu_mmc_init(bd_t * bis)152983e3700STom Rini int cpu_mmc_init(bd_t *bis)
153983e3700STom Rini {
154983e3700STom Rini int ret;
155983e3700STom Rini
156983e3700STom Rini ret = omap_mmc_init(0, 0, 0, -1, -1);
157983e3700STom Rini if (ret)
158983e3700STom Rini return ret;
159983e3700STom Rini
160983e3700STom Rini return omap_mmc_init(1, 0, 0, -1, -1);
161983e3700STom Rini }
162983e3700STom Rini #endif
163983e3700STom Rini
1647619badbSTero Kristo /*
1657619badbSTero Kristo * RTC only with DDR in self-refresh mode magic value, checked against during
1667619badbSTero Kristo * boot to see if we have a valid config. This should be in sync with the value
1677619badbSTero Kristo * that will be in drivers/soc/ti/pm33xx.c.
1687619badbSTero Kristo */
1697619badbSTero Kristo #define RTC_MAGIC_VAL 0x8cd0
1707619badbSTero Kristo
1717619badbSTero Kristo /* Board type field bit shift for RTC only with DDR in self-refresh mode */
1727619badbSTero Kristo #define RTC_BOARD_TYPE_SHIFT 16
1737619badbSTero Kristo
174983e3700STom Rini /* AM33XX has two MUSB controllers which can be host or gadget */
175983e3700STom Rini #if (defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)) && \
17619570221SMugunthan V N (defined(CONFIG_AM335X_USB0) || defined(CONFIG_AM335X_USB1)) && \
177*7a43dd7aSJean-Jacques Hiblot (!CONFIG_IS_ENABLED(DM_USB) || !CONFIG_IS_ENABLED(OF_CONTROL)) && \
178*7a43dd7aSJean-Jacques Hiblot (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_MUSB_NEW_SUPPORT))
179*7a43dd7aSJean-Jacques Hiblot
180*7a43dd7aSJean-Jacques Hiblot static struct musb_hdrc_config musb_config = {
181*7a43dd7aSJean-Jacques Hiblot .multipoint = 1,
182*7a43dd7aSJean-Jacques Hiblot .dyn_fifo = 1,
183*7a43dd7aSJean-Jacques Hiblot .num_eps = 16,
184*7a43dd7aSJean-Jacques Hiblot .ram_bits = 12,
185*7a43dd7aSJean-Jacques Hiblot };
186*7a43dd7aSJean-Jacques Hiblot
187*7a43dd7aSJean-Jacques Hiblot #if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
188*7a43dd7aSJean-Jacques Hiblot static struct ti_musb_platdata usb0 = {
189*7a43dd7aSJean-Jacques Hiblot .base = (void *)USB0_OTG_BASE,
190*7a43dd7aSJean-Jacques Hiblot .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
191*7a43dd7aSJean-Jacques Hiblot .plat = {
192*7a43dd7aSJean-Jacques Hiblot .config = &musb_config,
193*7a43dd7aSJean-Jacques Hiblot .power = 50,
194*7a43dd7aSJean-Jacques Hiblot .platform_ops = &musb_dsps_ops,
195*7a43dd7aSJean-Jacques Hiblot },
196*7a43dd7aSJean-Jacques Hiblot };
197*7a43dd7aSJean-Jacques Hiblot
198*7a43dd7aSJean-Jacques Hiblot static struct ti_musb_platdata usb1 = {
199*7a43dd7aSJean-Jacques Hiblot .base = (void *)USB1_OTG_BASE,
200*7a43dd7aSJean-Jacques Hiblot .ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
201*7a43dd7aSJean-Jacques Hiblot .plat = {
202*7a43dd7aSJean-Jacques Hiblot .config = &musb_config,
203*7a43dd7aSJean-Jacques Hiblot .power = 50,
204*7a43dd7aSJean-Jacques Hiblot .platform_ops = &musb_dsps_ops,
205*7a43dd7aSJean-Jacques Hiblot },
206*7a43dd7aSJean-Jacques Hiblot };
207*7a43dd7aSJean-Jacques Hiblot
208*7a43dd7aSJean-Jacques Hiblot U_BOOT_DEVICES(am33xx_usbs) = {
209*7a43dd7aSJean-Jacques Hiblot #if CONFIG_AM335X_USB0_MODE == MUSB_PERIPHERAL
210*7a43dd7aSJean-Jacques Hiblot { "ti-musb-peripheral", &usb0 },
211*7a43dd7aSJean-Jacques Hiblot #elif CONFIG_AM335X_USB0_MODE == MUSB_HOST
212*7a43dd7aSJean-Jacques Hiblot { "ti-musb-host", &usb0 },
213*7a43dd7aSJean-Jacques Hiblot #endif
214*7a43dd7aSJean-Jacques Hiblot #if CONFIG_AM335X_USB1_MODE == MUSB_PERIPHERAL
215*7a43dd7aSJean-Jacques Hiblot { "ti-musb-peripheral", &usb1 },
216*7a43dd7aSJean-Jacques Hiblot #elif CONFIG_AM335X_USB1_MODE == MUSB_HOST
217*7a43dd7aSJean-Jacques Hiblot { "ti-musb-host", &usb1 },
218*7a43dd7aSJean-Jacques Hiblot #endif
219*7a43dd7aSJean-Jacques Hiblot };
220*7a43dd7aSJean-Jacques Hiblot
arch_misc_init(void)221*7a43dd7aSJean-Jacques Hiblot int arch_misc_init(void)
222*7a43dd7aSJean-Jacques Hiblot {
223*7a43dd7aSJean-Jacques Hiblot return 0;
224*7a43dd7aSJean-Jacques Hiblot }
225*7a43dd7aSJean-Jacques Hiblot #else
226983e3700STom Rini static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
227983e3700STom Rini
228983e3700STom Rini /* USB 2.0 PHY Control */
229983e3700STom Rini #define CM_PHY_PWRDN (1 << 0)
230983e3700STom Rini #define CM_PHY_OTG_PWRDN (1 << 1)
231983e3700STom Rini #define OTGVDET_EN (1 << 19)
232983e3700STom Rini #define OTGSESSENDEN (1 << 20)
233983e3700STom Rini
am33xx_usb_set_phy_power(u8 on,u32 * reg_addr)234983e3700STom Rini static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr)
235983e3700STom Rini {
236983e3700STom Rini if (on) {
237983e3700STom Rini clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN,
238983e3700STom Rini OTGVDET_EN | OTGSESSENDEN);
239983e3700STom Rini } else {
240983e3700STom Rini clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN);
241983e3700STom Rini }
242983e3700STom Rini }
243983e3700STom Rini
244983e3700STom Rini #ifdef CONFIG_AM335X_USB0
am33xx_otg0_set_phy_power(struct udevice * dev,u8 on)2451cac34ceSMugunthan V N static void am33xx_otg0_set_phy_power(struct udevice *dev, u8 on)
246983e3700STom Rini {
247983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl0);
248983e3700STom Rini }
249983e3700STom Rini
250983e3700STom Rini struct omap_musb_board_data otg0_board_data = {
251983e3700STom Rini .set_phy_power = am33xx_otg0_set_phy_power,
252983e3700STom Rini };
253983e3700STom Rini
254983e3700STom Rini static struct musb_hdrc_platform_data otg0_plat = {
255983e3700STom Rini .mode = CONFIG_AM335X_USB0_MODE,
256983e3700STom Rini .config = &musb_config,
257983e3700STom Rini .power = 50,
258983e3700STom Rini .platform_ops = &musb_dsps_ops,
259983e3700STom Rini .board_data = &otg0_board_data,
260983e3700STom Rini };
261983e3700STom Rini #endif
262983e3700STom Rini
263983e3700STom Rini #ifdef CONFIG_AM335X_USB1
am33xx_otg1_set_phy_power(struct udevice * dev,u8 on)2641cac34ceSMugunthan V N static void am33xx_otg1_set_phy_power(struct udevice *dev, u8 on)
265983e3700STom Rini {
266983e3700STom Rini am33xx_usb_set_phy_power(on, &cdev->usb_ctrl1);
267983e3700STom Rini }
268983e3700STom Rini
269983e3700STom Rini struct omap_musb_board_data otg1_board_data = {
270983e3700STom Rini .set_phy_power = am33xx_otg1_set_phy_power,
271983e3700STom Rini };
272983e3700STom Rini
273983e3700STom Rini static struct musb_hdrc_platform_data otg1_plat = {
274983e3700STom Rini .mode = CONFIG_AM335X_USB1_MODE,
275983e3700STom Rini .config = &musb_config,
276983e3700STom Rini .power = 50,
277983e3700STom Rini .platform_ops = &musb_dsps_ops,
278983e3700STom Rini .board_data = &otg1_board_data,
279983e3700STom Rini };
280983e3700STom Rini #endif
281983e3700STom Rini
arch_misc_init(void)282983e3700STom Rini int arch_misc_init(void)
283983e3700STom Rini {
284983e3700STom Rini #ifdef CONFIG_AM335X_USB0
285983e3700STom Rini musb_register(&otg0_plat, &otg0_board_data,
286983e3700STom Rini (void *)USB0_OTG_BASE);
287983e3700STom Rini #endif
288983e3700STom Rini #ifdef CONFIG_AM335X_USB1
289983e3700STom Rini musb_register(&otg1_plat, &otg1_board_data,
290983e3700STom Rini (void *)USB1_OTG_BASE);
291983e3700STom Rini #endif
292409a81ddSAlexandru Gagniuc return 0;
293409a81ddSAlexandru Gagniuc }
294*7a43dd7aSJean-Jacques Hiblot #endif
295409a81ddSAlexandru Gagniuc
296409a81ddSAlexandru Gagniuc #else /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
297409a81ddSAlexandru Gagniuc
arch_misc_init(void)298409a81ddSAlexandru Gagniuc int arch_misc_init(void)
299409a81ddSAlexandru Gagniuc {
3003aec2648SMugunthan V N struct udevice *dev;
3013aec2648SMugunthan V N int ret;
3023aec2648SMugunthan V N
3033aec2648SMugunthan V N ret = uclass_first_device(UCLASS_MISC, &dev);
3043aec2648SMugunthan V N if (ret || !dev)
3053aec2648SMugunthan V N return ret;
306ba7916c7SMugunthan V N
307ba7916c7SMugunthan V N #if defined(CONFIG_DM_ETH) && defined(CONFIG_USB_ETHER)
308ba7916c7SMugunthan V N ret = usb_ether_init();
309ba7916c7SMugunthan V N if (ret) {
3109b643e31SMasahiro Yamada pr_err("USB ether init failed\n");
311ba7916c7SMugunthan V N return ret;
312ba7916c7SMugunthan V N }
313ba7916c7SMugunthan V N #endif
314409a81ddSAlexandru Gagniuc
315983e3700STom Rini return 0;
316983e3700STom Rini }
317983e3700STom Rini
318409a81ddSAlexandru Gagniuc #endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
319409a81ddSAlexandru Gagniuc
320983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT
3217619badbSTero Kristo
3227619badbSTero Kristo #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
3237619badbSTero Kristo (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
rtc32k_unlock(struct davinci_rtc * rtc)3247619badbSTero Kristo static void rtc32k_unlock(struct davinci_rtc *rtc)
3257619badbSTero Kristo {
3267619badbSTero Kristo /*
3277619badbSTero Kristo * Unlock the RTC's registers. For more details please see the
3287619badbSTero Kristo * RTC_SS section of the TRM. In order to unlock we need to
3297619badbSTero Kristo * write these specific values (keys) in this order.
3307619badbSTero Kristo */
3317619badbSTero Kristo writel(RTC_KICK0R_WE, &rtc->kick0r);
3327619badbSTero Kristo writel(RTC_KICK1R_WE, &rtc->kick1r);
3337619badbSTero Kristo }
3347619badbSTero Kristo #endif
3357619badbSTero Kristo
3367619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
3377619badbSTero Kristo /*
3387619badbSTero Kristo * Write contents of the RTC_SCRATCH1 register based on board type
3397619badbSTero Kristo * Two things are passed
3407619badbSTero Kristo * on. First 16 bits (0:15) are written with RTC_MAGIC value. Once the
3417619badbSTero Kristo * control gets to kernel, kernel reads the scratchpad register and gets to
3427619badbSTero Kristo * know that bootloader has rtc_only support.
3437619badbSTero Kristo *
3447619badbSTero Kristo * Second important thing is the board type (16:31). This is needed in the
3457619badbSTero Kristo * rtc_only boot where in we want to avoid costly i2c reads to eeprom to
3467619badbSTero Kristo * identify the board type and we go ahead and copy the board strings to
3477619badbSTero Kristo * am43xx_board_name.
3487619badbSTero Kristo */
update_rtc_magic(void)3497619badbSTero Kristo void update_rtc_magic(void)
3507619badbSTero Kristo {
3517619badbSTero Kristo struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
3527619badbSTero Kristo u32 magic = RTC_MAGIC_VAL;
3537619badbSTero Kristo
3547619badbSTero Kristo magic |= (rtc_only_get_board_type() << RTC_BOARD_TYPE_SHIFT);
3557619badbSTero Kristo
3567619badbSTero Kristo rtc32k_unlock(rtc);
3577619badbSTero Kristo
3587619badbSTero Kristo /* write magic */
3597619badbSTero Kristo writel(magic, &rtc->scratch1);
3607619badbSTero Kristo }
3617619badbSTero Kristo #endif
3627619badbSTero Kristo
363983e3700STom Rini /*
364983e3700STom Rini * In the case of non-SPL based booting we'll want to call these
365983e3700STom Rini * functions a tiny bit later as it will require gd to be set and cleared
366983e3700STom Rini * and that's not true in s_init in this case so we cannot do it there.
367983e3700STom Rini */
board_early_init_f(void)368983e3700STom Rini int board_early_init_f(void)
369983e3700STom Rini {
370983e3700STom Rini prcm_init();
371983e3700STom Rini set_mux_conf_regs();
3727619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
3737619badbSTero Kristo update_rtc_magic();
3747619badbSTero Kristo #endif
375983e3700STom Rini return 0;
376983e3700STom Rini }
377983e3700STom Rini
378983e3700STom Rini /*
379983e3700STom Rini * This function is the place to do per-board things such as ramp up the
380983e3700STom Rini * MPU clock frequency.
381983e3700STom Rini */
am33xx_spl_board_init(void)382983e3700STom Rini __weak void am33xx_spl_board_init(void)
383983e3700STom Rini {
384983e3700STom Rini }
385983e3700STom Rini
386983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
rtc32k_enable(void)387983e3700STom Rini static void rtc32k_enable(void)
388983e3700STom Rini {
389983e3700STom Rini struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
390983e3700STom Rini
3917619badbSTero Kristo rtc32k_unlock(rtc);
392983e3700STom Rini
393983e3700STom Rini /* Enable the RTC 32K OSC by setting bits 3 and 6. */
394983e3700STom Rini writel((1 << 3) | (1 << 6), &rtc->osc);
395983e3700STom Rini }
396983e3700STom Rini #endif
397983e3700STom Rini
uart_soft_reset(void)398983e3700STom Rini static void uart_soft_reset(void)
399983e3700STom Rini {
400983e3700STom Rini struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
401983e3700STom Rini u32 regval;
402983e3700STom Rini
403983e3700STom Rini regval = readl(&uart_base->uartsyscfg);
404983e3700STom Rini regval |= UART_RESET;
405983e3700STom Rini writel(regval, &uart_base->uartsyscfg);
406983e3700STom Rini while ((readl(&uart_base->uartsyssts) &
407983e3700STom Rini UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
408983e3700STom Rini ;
409983e3700STom Rini
410983e3700STom Rini /* Disable smart idle */
411983e3700STom Rini regval = readl(&uart_base->uartsyscfg);
412983e3700STom Rini regval |= UART_SMART_IDLE_EN;
413983e3700STom Rini writel(regval, &uart_base->uartsyscfg);
414983e3700STom Rini }
415983e3700STom Rini
watchdog_disable(void)416983e3700STom Rini static void watchdog_disable(void)
417983e3700STom Rini {
418983e3700STom Rini struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
419983e3700STom Rini
420983e3700STom Rini writel(0xAAAA, &wdtimer->wdtwspr);
421983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0)
422983e3700STom Rini ;
423983e3700STom Rini writel(0x5555, &wdtimer->wdtwspr);
424983e3700STom Rini while (readl(&wdtimer->wdtwwps) != 0x0)
425983e3700STom Rini ;
426983e3700STom Rini }
427983e3700STom Rini
4287619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
4297619badbSTero Kristo /*
4307619badbSTero Kristo * Check if we are executing rtc-only + DDR mode, and resume from it if needed
4317619badbSTero Kristo */
rtc_only(void)4327619badbSTero Kristo static void rtc_only(void)
4337619badbSTero Kristo {
4347619badbSTero Kristo struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE;
435025a0d40SRuss Dill struct prm_device_inst *prm_device =
436025a0d40SRuss Dill (struct prm_device_inst *)PRM_DEVICE_INST;
437025a0d40SRuss Dill
4387619badbSTero Kristo u32 scratch1;
4397619badbSTero Kristo void (*resume_func)(void);
4407619badbSTero Kristo
4417619badbSTero Kristo scratch1 = readl(&rtc->scratch1);
4427619badbSTero Kristo
4437619badbSTero Kristo /*
4447619badbSTero Kristo * Check RTC scratch against RTC_MAGIC_VAL, RTC_MAGIC_VAL is only
4457619badbSTero Kristo * written to this register when we want to wake up from RTC only
4467619badbSTero Kristo * with DDR in self-refresh mode. Contents of the RTC_SCRATCH1:
4477619badbSTero Kristo * bits 0-15: RTC_MAGIC_VAL
4487619badbSTero Kristo * bits 16-31: board type (needed for sdram_init)
4497619badbSTero Kristo */
4507619badbSTero Kristo if ((scratch1 & 0xffff) != RTC_MAGIC_VAL)
4517619badbSTero Kristo return;
4527619badbSTero Kristo
4537619badbSTero Kristo rtc32k_unlock(rtc);
4547619badbSTero Kristo
4557619badbSTero Kristo /* Clear RTC magic */
4567619badbSTero Kristo writel(0, &rtc->scratch1);
4577619badbSTero Kristo
4587619badbSTero Kristo /*
4597619badbSTero Kristo * Update board type based on value stored on RTC_SCRATCH1, this
4607619badbSTero Kristo * is done so that we don't need to read the board type from eeprom
4617619badbSTero Kristo * over i2c bus which is expensive
4627619badbSTero Kristo */
4637619badbSTero Kristo rtc_only_update_board_type(scratch1 >> RTC_BOARD_TYPE_SHIFT);
4647619badbSTero Kristo
465025a0d40SRuss Dill /*
466025a0d40SRuss Dill * Enable EMIF_DEVOFF in PRCM_PRM_EMIF_CTRL to indicate to EMIF we
467025a0d40SRuss Dill * are resuming from self-refresh. This avoids an unnecessary re-init
468025a0d40SRuss Dill * of the DDR. The re-init takes time and we would need to wait for
469025a0d40SRuss Dill * it to complete before accessing DDR to avoid L3 NOC errors.
470025a0d40SRuss Dill */
471025a0d40SRuss Dill writel(EMIF_CTRL_DEVOFF, &prm_device->emif_ctrl);
472025a0d40SRuss Dill
4737619badbSTero Kristo rtc_only_prcm_init();
4747619badbSTero Kristo sdram_init();
4757619badbSTero Kristo
476025a0d40SRuss Dill /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */
477025a0d40SRuss Dill writel(0, &prm_device->emif_ctrl);
478025a0d40SRuss Dill
4797619badbSTero Kristo resume_func = (void *)readl(&rtc->scratch0);
4807619badbSTero Kristo if (resume_func)
4817619badbSTero Kristo resume_func();
4827619badbSTero Kristo }
4837619badbSTero Kristo #endif
4847619badbSTero Kristo
s_init(void)485983e3700STom Rini void s_init(void)
486983e3700STom Rini {
4877619badbSTero Kristo #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT)
4887619badbSTero Kristo rtc_only();
4897619badbSTero Kristo #endif
490983e3700STom Rini }
491983e3700STom Rini
early_system_init(void)492983e3700STom Rini void early_system_init(void)
493983e3700STom Rini {
494983e3700STom Rini /*
495983e3700STom Rini * The ROM will only have set up sufficient pinmux to allow for the
496983e3700STom Rini * first 4KiB NOR to be read, we must finish doing what we know of
497983e3700STom Rini * the NOR mux in this space in order to continue.
498983e3700STom Rini */
499983e3700STom Rini #ifdef CONFIG_NOR_BOOT
500983e3700STom Rini enable_norboot_pin_mux();
501983e3700STom Rini #endif
502983e3700STom Rini watchdog_disable();
503983e3700STom Rini set_uart_mux_conf();
504983e3700STom Rini setup_early_clocks();
505983e3700STom Rini uart_soft_reset();
5064bd754d8SLokesh Vutla #ifdef CONFIG_SPL_BUILD
5074bd754d8SLokesh Vutla /*
5084bd754d8SLokesh Vutla * Save the boot parameters passed from romcode.
5094bd754d8SLokesh Vutla * We cannot delay the saving further than this,
5104bd754d8SLokesh Vutla * to prevent overwrites.
5114bd754d8SLokesh Vutla */
5124bd754d8SLokesh Vutla save_omap_boot_params();
5134bd754d8SLokesh Vutla #endif
514878d8856SLokesh Vutla #ifdef CONFIG_DEBUG_UART_OMAP
515878d8856SLokesh Vutla debug_uart_init();
516878d8856SLokesh Vutla #endif
5172b30b38bSJean-Jacques Hiblot
518b442e16bSFaiz Abbas #ifdef CONFIG_SPL_BUILD
519b442e16bSFaiz Abbas spl_early_init();
520b442e16bSFaiz Abbas #endif
5212b30b38bSJean-Jacques Hiblot
5222b30b38bSJean-Jacques Hiblot #ifdef CONFIG_TI_I2C_BOARD_DETECT
5232b30b38bSJean-Jacques Hiblot do_board_detect();
5242b30b38bSJean-Jacques Hiblot #endif
5252b30b38bSJean-Jacques Hiblot
526983e3700STom Rini #if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
527983e3700STom Rini /* Enable RTC32K clock */
528983e3700STom Rini rtc32k_enable();
529983e3700STom Rini #endif
530983e3700STom Rini }
531983e3700STom Rini
532983e3700STom Rini #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)533983e3700STom Rini void board_init_f(ulong dummy)
534983e3700STom Rini {
53500bbe96eSSemen Protsenko hw_data_init();
536983e3700STom Rini early_system_init();
537983e3700STom Rini board_early_init_f();
538983e3700STom Rini sdram_init();
53986282798SLokesh Vutla /* dram_init must store complete ramsize in gd->ram_size */
54086282798SLokesh Vutla gd->ram_size = get_ram_size(
54186282798SLokesh Vutla (void *)CONFIG_SYS_SDRAM_BASE,
54286282798SLokesh Vutla CONFIG_MAX_RAM_BANK_SIZE);
543983e3700STom Rini }
544983e3700STom Rini #endif
545983e3700STom Rini
546983e3700STom Rini #endif
547983e3700STom Rini
arch_cpu_init_dm(void)548983e3700STom Rini int arch_cpu_init_dm(void)
549983e3700STom Rini {
55000bbe96eSSemen Protsenko hw_data_init();
551983e3700STom Rini #ifndef CONFIG_SKIP_LOWLEVEL_INIT
552983e3700STom Rini early_system_init();
553983e3700STom Rini #endif
554983e3700STom Rini return 0;
555983e3700STom Rini }
556