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Searched refs:reg_base (Results 1 – 25 of 43) sorted by relevance

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/openbmc/u-boot/board/sunxi/
H A Dahci.c17 static int sunxi_ahci_phy_init(u8 *reg_base) in sunxi_ahci_phy_init() argument
22 writel(0, reg_base + AHCI_RWCR); in sunxi_ahci_phy_init()
25 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19); in sunxi_ahci_phy_init()
26 clrsetbits_le32(reg_base + AHCI_PHYCS0R, in sunxi_ahci_phy_init()
29 clrsetbits_le32(reg_base + AHCI_PHYCS1R, in sunxi_ahci_phy_init()
32 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15)); in sunxi_ahci_phy_init()
33 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19)); in sunxi_ahci_phy_init()
34 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20)); in sunxi_ahci_phy_init()
35 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5)); in sunxi_ahci_phy_init()
38 setbits_le32(reg_base + AHCI_PHYCS0R, (0x1 << 19)); in sunxi_ahci_phy_init()
[all …]
/openbmc/u-boot/drivers/spi/
H A Dcadence_qspi_apb.c166 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \ argument
167 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
170 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \ argument
171 (((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >> \
187 void cadence_qspi_apb_controller_enable(void *reg_base) in cadence_qspi_apb_controller_enable() argument
190 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
192 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_enable()
195 void cadence_qspi_apb_controller_disable(void *reg_base) in cadence_qspi_apb_controller_disable() argument
198 reg = readl(reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
200 writel(reg, reg_base + CQSPI_REG_CONFIG); in cadence_qspi_apb_controller_disable()
[all …]
H A Dcadence_qspi.h67 void cadence_qspi_apb_chipselect(void *reg_base,
69 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
70 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
72 void cadence_qspi_apb_delay(void *reg_base,
76 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy);
77 void cadence_qspi_apb_readdata_capture(void *reg_base,
H A Datmel_spi.c242 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_claim_bus() local
262 writel(csrx, &reg_base->csr[cs]); in atmel_spi_claim_bus()
269 writel(mode, &reg_base->mr); in atmel_spi_claim_bus()
271 writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr); in atmel_spi_claim_bus()
321 struct at91_spi *reg_base = bus_plat->regs; in atmel_spi_xfer() local
363 readl(&reg_base->rdr); in atmel_spi_xfer()
367 status = readl(&reg_base->sr); in atmel_spi_xfer()
377 writel(value, &reg_base->tdr); in atmel_spi_xfer()
382 value = readl(&reg_base->rdr); in atmel_spi_xfer()
395 wait_for_bit_le32(&reg_base->sr, in atmel_spi_xfer()
/openbmc/u-boot/drivers/mmc/
H A Dkona_sdhci.c81 void *reg_base; in kona_sdhci_init() local
91 reg_base = (void *)CONFIG_SYS_SDIO_BASE0; in kona_sdhci_init()
92 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK, in kona_sdhci_init()
96 reg_base = (void *)CONFIG_SYS_SDIO_BASE1; in kona_sdhci_init()
97 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK, in kona_sdhci_init()
101 reg_base = (void *)CONFIG_SYS_SDIO_BASE2; in kona_sdhci_init()
102 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK, in kona_sdhci_init()
106 reg_base = (void *)CONFIG_SYS_SDIO_BASE3; in kona_sdhci_init()
107 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK, in kona_sdhci_init()
121 host->ioaddr = reg_base; in kona_sdhci_init()
H A Ddavinci_mmc.c36 struct davinci_mmc_regs *reg_base; /* Register base address */ member
62 struct davinci_mmc_regs *regs = host->reg_base;
168 volatile struct davinci_mmc_regs *regs = host->reg_base;
362 struct davinci_mmc_regs *regs = host->reg_base;
398 struct davinci_mmc_regs *regs = host->reg_base;
405 struct davinci_mmc_regs *regs = host->reg_base;
510 priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll-base-ld20.c31 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, in uniphier_ld20_sscpll_init() argument
37 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_init()
68 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) in uniphier_ld20_sscpll_ssc_en() argument
73 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_ssc_en()
86 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) in uniphier_ld20_sscpll_set_regi() argument
91 base = ioremap(reg_base, SZ_16); in uniphier_ld20_sscpll_set_regi()
105 int uniphier_ld20_vpll27_init(unsigned long reg_base) in uniphier_ld20_vpll27_init() argument
110 base = ioremap(reg_base, SZ_16); in uniphier_ld20_vpll27_init()
131 int uniphier_ld20_dspll_init(unsigned long reg_base) in uniphier_ld20_dspll_init() argument
136 base = ioremap(reg_base, SZ_16); in uniphier_ld20_dspll_init()
H A Dpll.h14 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
16 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
17 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
18 int uniphier_ld20_vpll27_init(unsigned long reg_base);
19 int uniphier_ld20_dspll_init(unsigned long reg_base);
/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c19 void *reg_base = bus->priv; in pfe_write_addr() local
30 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
35 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) { in pfe_write_addr()
45 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_write_addr()
53 void *reg_base = bus->priv; in pfe_phy_read() local
78 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
83 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) { in pfe_phy_read()
93 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG); in pfe_phy_read()
98 val = (u16)readl(reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
99 debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base, in pfe_phy_read()
[all …]
/openbmc/u-boot/drivers/usb/musb-new/
H A Dam35x.c94 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_enable() local
101 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask); in am35x_musb_enable()
102 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK); in am35x_musb_enable()
106 musb_writel(reg_base, CORE_INTR_SRC_SET_REG, in am35x_musb_enable()
118 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_disable() local
120 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK); in am35x_musb_disable()
121 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG, in am35x_musb_disable()
124 musb_writel(reg_base, USB_END_OF_INTR_REG, 0); in am35x_musb_disable()
226 void __iomem *reg_base = musb->ctrl_base; in am35x_musb_interrupt() local
251 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG); in am35x_musb_interrupt()
[all …]
H A Dmusb_dsps.c158 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_enable() local
166 dsps_writel(reg_base, wrp->epintr_set, epmask); in dsps_musb_enable()
167 dsps_writel(reg_base, wrp->coreintr_set, coremask); in dsps_musb_enable()
171 dsps_writel(reg_base, wrp->coreintr_set, in dsps_musb_enable()
188 void __iomem *reg_base = musb->ctrl_base; in dsps_musb_disable() local
190 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap); in dsps_musb_disable()
191 dsps_writel(reg_base, wrp->epintr_clear, in dsps_musb_disable()
194 dsps_writel(reg_base, wrp->eoi, 0); in dsps_musb_disable()
295 void __iomem *reg_base = musb->ctrl_base; in dsps_interrupt() local
311 epintr = dsps_readl(reg_base, wrp->epintr_status); in dsps_interrupt()
[all …]
/openbmc/qemu/hw/intc/
H A Dopenpic_kvm.c123 uint64_t reg_base; in kvm_openpic_region_add() local
139 reg_base = section->offset_within_address_space; in kvm_openpic_region_add()
140 opp->mapped = reg_base; in kvm_openpic_region_add()
144 attr.addr = (uint64_t)(unsigned long)&reg_base; in kvm_openpic_region_add()
149 strerror(errno), reg_base); in kvm_openpic_region_add()
159 uint64_t reg_base = 0; in kvm_openpic_region_del() local
178 attr.addr = (uint64_t)(unsigned long)&reg_base; in kvm_openpic_region_del()
183 strerror(errno), reg_base); in kvm_openpic_region_del()
/openbmc/qemu/tests/qtest/
H A Dm48t59-test.c29 static uint16_t reg_base = 0x1ff0; /* 0x7f0 for m48t02 */ variable
36 return qtest_readb(s, base + (uint32_t)reg_base + (uint32_t)reg); in cmos_read_mmio()
43 qtest_writeb(s, base + (uint32_t)reg_base + (uint32_t)reg, data); in cmos_write_mmio()
48 qtest_outw(s, base + 0, reg_base + (uint16_t)reg); in cmos_read_ioio()
54 qtest_outw(s, base + 0, reg_base + (uint16_t)reg); in cmos_write_ioio()
/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl-at91-pio4.c25 struct atmel_pio4_port *reg_base; member
99 (struct atmel_pio4_port *)((u32)plat->reg_base + in atmel_pio4_bank_base()
164 plat->reg_base = (struct atmel_pio4_port *)addr_base; in atmel_pinctrl_probe()
/openbmc/u-boot/drivers/clk/at91/
H A Dclk-plladiv.c22 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_get_rate()
41 struct at91_pmc *pmc = plat->reg_base; in at91_plladiv_clk_set_rate()
H A Dpmc.c41 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev); in at91_pmc_core_probe()
116 plat->reg_base = (struct at91_pmc *)devfdt_get_addr_ptr(dev_pmc); in at91_clk_probe()
H A Dpmc.h13 struct at91_pmc *reg_base; member
H A Dclk-usb.c26 struct at91_pmc *pmc = plat->reg_base; in at91_usb_clk_get_rate()
47 struct at91_pmc *pmc = plat->reg_base; in at91_usb_clk_set_rate()
H A Dclk-plla.c19 struct at91_pmc *pmc = plat->reg_base; in plla_clk_enable()
H A Dclk-main.c19 struct at91_pmc *pmc = plat->reg_base; in main_osc_clk_enable()
H A Dclk-generated.c51 struct at91_pmc *pmc = plat->reg_base; in generic_clk_get_rate()
79 struct at91_pmc *pmc = plat->reg_base; in generic_clk_set_rate()
H A Dclk-h32mx.c22 struct at91_pmc *pmc = plat->reg_base; in sama5d4_h32mx_clk_get_rate()
/openbmc/u-boot/board/freescale/ls1012afrdm/
H A Deth.c54 mac_mdio_info.reg_base = (void *)EMAC1_BASE_ADDR; in pfe_eth_board_init()
67 mac_mdio_info.reg_base = (void *)EMAC2_BASE_ADDR; in pfe_eth_board_init()
/openbmc/u-boot/drivers/ram/aspeed/
H A Dsdram_ast2600.c238 u32 reg_base = (u32)info->phy_setting; in ast2600_sdramphy_init() local
249 if (addr < reg_base) { in ast2600_sdramphy_init()
275 u32 reg_base = (u32)info->phy_status; in ast2600_sdramphy_check_status() local
280 value = readl(reg_base + 0x00); in ast2600_sdramphy_check_status()
289 value = readl(reg_base + 0x30); in ast2600_sdramphy_check_status()
295 value = readl(reg_base + 0x68); in ast2600_sdramphy_check_status()
306 value = readl(reg_base + 0xC8); in ast2600_sdramphy_check_status()
315 value = readl(reg_base + 0x7c); in ast2600_sdramphy_check_status()
327 value = readl(reg_base + 0x88); in ast2600_sdramphy_check_status()
336 value = readl(reg_base + 0x90); in ast2600_sdramphy_check_status()
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci_ftpci100.c19 unsigned int reg_base; member
228 priv->reg_base = CONFIG_FTPCI100_BASE; in ftpci_preinit()
233 ftpci100 = (struct ftpci100_ahbc *)priv->reg_base; in ftpci_preinit()

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