xref: /openbmc/u-boot/arch/arm/mach-uniphier/clk/pll.h (revision e8f80a5a)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
26a3e4274SMasahiro Yamada /*
36a3e4274SMasahiro Yamada  * Copyright (C) 2016 Socionext Inc.
46a3e4274SMasahiro Yamada  *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
56a3e4274SMasahiro Yamada  */
66a3e4274SMasahiro Yamada 
76a3e4274SMasahiro Yamada #ifndef MACH_PLL_H
86a3e4274SMasahiro Yamada #define MACH_PLL_H
96a3e4274SMasahiro Yamada 
10682e09ffSMasahiro Yamada #define UNIPHIER_PLL_FREQ_DEFAULT	(0)
11682e09ffSMasahiro Yamada 
126a3e4274SMasahiro Yamada void uniphier_ld4_dpll_ssc_en(void);
136a3e4274SMasahiro Yamada 
14682e09ffSMasahiro Yamada int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
15682e09ffSMasahiro Yamada 			      unsigned int ssc_rate, unsigned int divn);
16682e09ffSMasahiro Yamada int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
17bc647958SMasahiro Yamada int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
18682e09ffSMasahiro Yamada int uniphier_ld20_vpll27_init(unsigned long reg_base);
19682e09ffSMasahiro Yamada int uniphier_ld20_dspll_init(unsigned long reg_base);
20682e09ffSMasahiro Yamada 
216a3e4274SMasahiro Yamada #endif /* MACH_PLL_H */
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