183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
257418d21SSandeep Paulraj /*
357418d21SSandeep Paulraj * Davinci MMC Controller Driver
457418d21SSandeep Paulraj *
557418d21SSandeep Paulraj * Copyright (C) 2010 Texas Instruments Incorporated
657418d21SSandeep Paulraj */
757418d21SSandeep Paulraj
857418d21SSandeep Paulraj #include <config.h>
957418d21SSandeep Paulraj #include <common.h>
10df6565c3SAdam Ford #include <dm.h>
11915ffa52SJaehoon Chung #include <errno.h>
1257418d21SSandeep Paulraj #include <mmc.h>
13df6565c3SAdam Ford #include <command.h>
1457418d21SSandeep Paulraj #include <part.h>
1557418d21SSandeep Paulraj #include <malloc.h>
1657418d21SSandeep Paulraj #include <asm/io.h>
1757418d21SSandeep Paulraj #include <asm/arch/sdmmc_defs.h>
18*04355de7SAdam Ford #include <asm-generic/gpio.h>
1957418d21SSandeep Paulraj
2057418d21SSandeep Paulraj #define DAVINCI_MAX_BLOCKS (32)
2157418d21SSandeep Paulraj #define WATCHDOG_COUNT (100000)
2257418d21SSandeep Paulraj
2357418d21SSandeep Paulraj #define get_val(addr) REG(addr)
2457418d21SSandeep Paulraj #define set_val(addr, val) REG(addr) = (val)
2557418d21SSandeep Paulraj #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
2657418d21SSandeep Paulraj #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
2757418d21SSandeep Paulraj
28df6565c3SAdam Ford #ifdef CONFIG_DM_MMC
29df6565c3SAdam Ford struct davinci_of_data {
30df6565c3SAdam Ford const char *name;
31df6565c3SAdam Ford u8 version;
32df6565c3SAdam Ford };
33df6565c3SAdam Ford
34df6565c3SAdam Ford /* Davinci MMC board definitions */
35df6565c3SAdam Ford struct davinci_mmc_priv {
36df6565c3SAdam Ford struct davinci_mmc_regs *reg_base; /* Register base address */
37df6565c3SAdam Ford uint input_clk; /* Input clock to MMC controller */
38df6565c3SAdam Ford uint version; /* MMC Controller version */
39*04355de7SAdam Ford struct gpio_desc cd_gpio; /* Card Detect GPIO */
40*04355de7SAdam Ford struct gpio_desc wp_gpio; /* Write Protect GPIO */
41df6565c3SAdam Ford };
42df6565c3SAdam Ford
43df6565c3SAdam Ford struct davinci_mmc_plat
44df6565c3SAdam Ford {
45df6565c3SAdam Ford struct mmc_config cfg;
46df6565c3SAdam Ford struct mmc mmc;
47df6565c3SAdam Ford };
48df6565c3SAdam Ford #endif
49df6565c3SAdam Ford
5057418d21SSandeep Paulraj /* Set davinci clock prescalar value based on the required clock in HZ */
51df6565c3SAdam Ford #if !CONFIG_IS_ENABLED(DM_MMC)
dmmc_set_clock(struct mmc * mmc,uint clock)5257418d21SSandeep Paulraj static void dmmc_set_clock(struct mmc *mmc, uint clock)
5357418d21SSandeep Paulraj {
5457418d21SSandeep Paulraj struct davinci_mmc *host = mmc->priv;
55df6565c3SAdam Ford #else
56df6565c3SAdam Ford
57df6565c3SAdam Ford static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
58df6565c3SAdam Ford {
59df6565c3SAdam Ford struct davinci_mmc_priv *host = dev_get_priv(dev);
60df6565c3SAdam Ford struct mmc *mmc = mmc_get_mmc_dev(dev);
61df6565c3SAdam Ford #endif
6257418d21SSandeep Paulraj struct davinci_mmc_regs *regs = host->reg_base;
6357418d21SSandeep Paulraj uint clkrt, sysclk2, act_clock;
6457418d21SSandeep Paulraj
6593bfd616SPantelis Antoniou if (clock < mmc->cfg->f_min)
6693bfd616SPantelis Antoniou clock = mmc->cfg->f_min;
6793bfd616SPantelis Antoniou if (clock > mmc->cfg->f_max)
6893bfd616SPantelis Antoniou clock = mmc->cfg->f_max;
6957418d21SSandeep Paulraj
7057418d21SSandeep Paulraj set_val(®s->mmcclk, 0);
7157418d21SSandeep Paulraj sysclk2 = host->input_clk;
7257418d21SSandeep Paulraj clkrt = (sysclk2 / (2 * clock)) - 1;
7357418d21SSandeep Paulraj
7457418d21SSandeep Paulraj /* Calculate the actual clock for the divider used */
7557418d21SSandeep Paulraj act_clock = (sysclk2 / (2 * (clkrt + 1)));
7657418d21SSandeep Paulraj
7757418d21SSandeep Paulraj /* Adjust divider if actual clock exceeds the required clock */
7857418d21SSandeep Paulraj if (act_clock > clock)
7957418d21SSandeep Paulraj clkrt++;
8057418d21SSandeep Paulraj
8157418d21SSandeep Paulraj /* check clock divider boundary and correct it */
8257418d21SSandeep Paulraj if (clkrt > 0xFF)
8357418d21SSandeep Paulraj clkrt = 0xFF;
8457418d21SSandeep Paulraj
8557418d21SSandeep Paulraj set_val(®s->mmcclk, (clkrt | MMCCLK_CLKEN));
8657418d21SSandeep Paulraj }
8757418d21SSandeep Paulraj
8857418d21SSandeep Paulraj /* Status bit wait loop for MMCST1 */
8957418d21SSandeep Paulraj static int
9057418d21SSandeep Paulraj dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
9157418d21SSandeep Paulraj {
9279b05d59SHeiko Schocher uint wdog = WATCHDOG_COUNT;
9379b05d59SHeiko Schocher
9457418d21SSandeep Paulraj while (--wdog && ((get_val(®s->mmcst1) & status) != status))
9557418d21SSandeep Paulraj udelay(10);
9657418d21SSandeep Paulraj
9757418d21SSandeep Paulraj if (!(get_val(®s->mmcctl) & MMCCTL_WIDTH_4_BIT))
9857418d21SSandeep Paulraj udelay(100);
9957418d21SSandeep Paulraj
10057418d21SSandeep Paulraj if (wdog == 0)
101915ffa52SJaehoon Chung return -ECOMM;
10257418d21SSandeep Paulraj
10357418d21SSandeep Paulraj return 0;
10457418d21SSandeep Paulraj }
10557418d21SSandeep Paulraj
10657418d21SSandeep Paulraj /* Busy bit wait loop for MMCST1 */
10757418d21SSandeep Paulraj static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
10857418d21SSandeep Paulraj {
10979b05d59SHeiko Schocher uint wdog = WATCHDOG_COUNT;
11057418d21SSandeep Paulraj
11157418d21SSandeep Paulraj while (--wdog && (get_val(®s->mmcst1) & MMCST1_BUSY))
11257418d21SSandeep Paulraj udelay(10);
11357418d21SSandeep Paulraj
11457418d21SSandeep Paulraj if (wdog == 0)
115915ffa52SJaehoon Chung return -ECOMM;
11657418d21SSandeep Paulraj
11757418d21SSandeep Paulraj return 0;
11857418d21SSandeep Paulraj }
11957418d21SSandeep Paulraj
12057418d21SSandeep Paulraj /* Status bit wait loop for MMCST0 - Checks for error bits as well */
12157418d21SSandeep Paulraj static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
12257418d21SSandeep Paulraj uint *cur_st, uint st_ready, uint st_error)
12357418d21SSandeep Paulraj {
12457418d21SSandeep Paulraj uint wdog = WATCHDOG_COUNT;
12557418d21SSandeep Paulraj uint mmcstatus = *cur_st;
12657418d21SSandeep Paulraj
12757418d21SSandeep Paulraj while (wdog--) {
12857418d21SSandeep Paulraj if (mmcstatus & st_ready) {
12957418d21SSandeep Paulraj *cur_st = mmcstatus;
13057418d21SSandeep Paulraj mmcstatus = get_val(®s->mmcst1);
13157418d21SSandeep Paulraj return 0;
13257418d21SSandeep Paulraj } else if (mmcstatus & st_error) {
13357418d21SSandeep Paulraj if (mmcstatus & MMCST0_TOUTRS)
134915ffa52SJaehoon Chung return -ETIMEDOUT;
13557418d21SSandeep Paulraj printf("[ ST0 ERROR %x]\n", mmcstatus);
13657418d21SSandeep Paulraj /*
13757418d21SSandeep Paulraj * Ignore CRC errors as some MMC cards fail to
13857418d21SSandeep Paulraj * initialize on DM365-EVM on the SD1 slot
13957418d21SSandeep Paulraj */
14057418d21SSandeep Paulraj if (mmcstatus & MMCST0_CRCRS)
14157418d21SSandeep Paulraj return 0;
142915ffa52SJaehoon Chung return -ECOMM;
14357418d21SSandeep Paulraj }
14457418d21SSandeep Paulraj udelay(10);
14557418d21SSandeep Paulraj
14657418d21SSandeep Paulraj mmcstatus = get_val(®s->mmcst0);
14757418d21SSandeep Paulraj }
14857418d21SSandeep Paulraj
14957418d21SSandeep Paulraj printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
15057418d21SSandeep Paulraj get_val(®s->mmcst1));
151915ffa52SJaehoon Chung return -ECOMM;
15257418d21SSandeep Paulraj }
15357418d21SSandeep Paulraj
15457418d21SSandeep Paulraj /*
155df6565c3SAdam Ford * Sends a command out on the bus. Takes the device pointer,
15657418d21SSandeep Paulraj * a command pointer, and an optional data pointer.
15757418d21SSandeep Paulraj */
158df6565c3SAdam Ford #if !CONFIG_IS_ENABLED(DM_MMC)
159df6565c3SAdam Ford static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
16057418d21SSandeep Paulraj {
16157418d21SSandeep Paulraj struct davinci_mmc *host = mmc->priv;
162df6565c3SAdam Ford #else
163df6565c3SAdam Ford static int
164df6565c3SAdam Ford davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
165df6565c3SAdam Ford {
166df6565c3SAdam Ford struct davinci_mmc_priv *host = dev_get_priv(dev);
167df6565c3SAdam Ford #endif
16857418d21SSandeep Paulraj volatile struct davinci_mmc_regs *regs = host->reg_base;
16957418d21SSandeep Paulraj uint mmcstatus, status_rdy, status_err;
17057418d21SSandeep Paulraj uint i, cmddata, bytes_left = 0;
17157418d21SSandeep Paulraj int fifo_words, fifo_bytes, err;
17257418d21SSandeep Paulraj char *data_buf = NULL;
17357418d21SSandeep Paulraj
17457418d21SSandeep Paulraj /* Clear status registers */
17557418d21SSandeep Paulraj mmcstatus = get_val(®s->mmcst0);
17657418d21SSandeep Paulraj fifo_words = (host->version == MMC_CTLR_VERSION_2) ? 16 : 8;
17757418d21SSandeep Paulraj fifo_bytes = fifo_words << 2;
17857418d21SSandeep Paulraj
17957418d21SSandeep Paulraj /* Wait for any previous busy signal to be cleared */
18057418d21SSandeep Paulraj dmmc_busy_wait(regs);
18157418d21SSandeep Paulraj
18257418d21SSandeep Paulraj cmddata = cmd->cmdidx;
18357418d21SSandeep Paulraj cmddata |= MMCCMD_PPLEN;
18457418d21SSandeep Paulraj
18557418d21SSandeep Paulraj /* Send init clock for CMD0 */
18657418d21SSandeep Paulraj if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
18757418d21SSandeep Paulraj cmddata |= MMCCMD_INITCK;
18857418d21SSandeep Paulraj
18957418d21SSandeep Paulraj switch (cmd->resp_type) {
19057418d21SSandeep Paulraj case MMC_RSP_R1b:
19157418d21SSandeep Paulraj cmddata |= MMCCMD_BSYEXP;
19257418d21SSandeep Paulraj /* Fall-through */
19357418d21SSandeep Paulraj case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
19457418d21SSandeep Paulraj cmddata |= MMCCMD_RSPFMT_R1567;
19557418d21SSandeep Paulraj break;
19657418d21SSandeep Paulraj case MMC_RSP_R2:
19757418d21SSandeep Paulraj cmddata |= MMCCMD_RSPFMT_R2;
19857418d21SSandeep Paulraj break;
19957418d21SSandeep Paulraj case MMC_RSP_R3: /* R3, R4 */
20057418d21SSandeep Paulraj cmddata |= MMCCMD_RSPFMT_R3;
20157418d21SSandeep Paulraj break;
20257418d21SSandeep Paulraj }
20357418d21SSandeep Paulraj
20457418d21SSandeep Paulraj set_val(®s->mmcim, 0);
20557418d21SSandeep Paulraj
20657418d21SSandeep Paulraj if (data) {
20757418d21SSandeep Paulraj /* clear previous data transfer if any and set new one */
20857418d21SSandeep Paulraj bytes_left = (data->blocksize * data->blocks);
20957418d21SSandeep Paulraj
21057418d21SSandeep Paulraj /* Reset FIFO - Always use 32 byte fifo threshold */
21157418d21SSandeep Paulraj set_val(®s->mmcfifoctl,
21257418d21SSandeep Paulraj (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
21357418d21SSandeep Paulraj
21457418d21SSandeep Paulraj if (host->version == MMC_CTLR_VERSION_2)
21557418d21SSandeep Paulraj cmddata |= MMCCMD_DMATRIG;
21657418d21SSandeep Paulraj
21757418d21SSandeep Paulraj cmddata |= MMCCMD_WDATX;
21857418d21SSandeep Paulraj if (data->flags == MMC_DATA_READ) {
21957418d21SSandeep Paulraj set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
22057418d21SSandeep Paulraj } else if (data->flags == MMC_DATA_WRITE) {
22157418d21SSandeep Paulraj set_val(®s->mmcfifoctl,
22257418d21SSandeep Paulraj (MMCFIFOCTL_FIFOLEV |
22357418d21SSandeep Paulraj MMCFIFOCTL_FIFODIR));
22457418d21SSandeep Paulraj cmddata |= MMCCMD_DTRW;
22557418d21SSandeep Paulraj }
22657418d21SSandeep Paulraj
22757418d21SSandeep Paulraj set_val(®s->mmctod, 0xFFFF);
22857418d21SSandeep Paulraj set_val(®s->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
22957418d21SSandeep Paulraj set_val(®s->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
23057418d21SSandeep Paulraj
23157418d21SSandeep Paulraj if (data->flags == MMC_DATA_WRITE) {
23257418d21SSandeep Paulraj uint val;
23357418d21SSandeep Paulraj data_buf = (char *)data->src;
23457418d21SSandeep Paulraj /* For write, fill FIFO with data before issue of CMD */
23557418d21SSandeep Paulraj for (i = 0; (i < fifo_words) && bytes_left; i++) {
23657418d21SSandeep Paulraj memcpy((char *)&val, data_buf, 4);
23757418d21SSandeep Paulraj set_val(®s->mmcdxr, val);
23857418d21SSandeep Paulraj data_buf += 4;
23957418d21SSandeep Paulraj bytes_left -= 4;
24057418d21SSandeep Paulraj }
24157418d21SSandeep Paulraj }
24257418d21SSandeep Paulraj } else {
24357418d21SSandeep Paulraj set_val(®s->mmcblen, 0);
24457418d21SSandeep Paulraj set_val(®s->mmcnblk, 0);
24557418d21SSandeep Paulraj }
24657418d21SSandeep Paulraj
24757418d21SSandeep Paulraj set_val(®s->mmctor, 0x1FFF);
24857418d21SSandeep Paulraj
24957418d21SSandeep Paulraj /* Send the command */
25057418d21SSandeep Paulraj set_val(®s->mmcarghl, cmd->cmdarg);
25157418d21SSandeep Paulraj set_val(®s->mmccmd, cmddata);
25257418d21SSandeep Paulraj
25357418d21SSandeep Paulraj status_rdy = MMCST0_RSPDNE;
25457418d21SSandeep Paulraj status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
25557418d21SSandeep Paulraj MMCST0_CRCWR | MMCST0_CRCRD);
25657418d21SSandeep Paulraj if (cmd->resp_type & MMC_RSP_CRC)
25757418d21SSandeep Paulraj status_err |= MMCST0_CRCRS;
25857418d21SSandeep Paulraj
25957418d21SSandeep Paulraj mmcstatus = get_val(®s->mmcst0);
26057418d21SSandeep Paulraj err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
26157418d21SSandeep Paulraj if (err)
26257418d21SSandeep Paulraj return err;
26357418d21SSandeep Paulraj
26457418d21SSandeep Paulraj /* For R1b wait for busy done */
26557418d21SSandeep Paulraj if (cmd->resp_type == MMC_RSP_R1b)
26657418d21SSandeep Paulraj dmmc_busy_wait(regs);
26757418d21SSandeep Paulraj
26857418d21SSandeep Paulraj /* Collect response from controller for specific commands */
26957418d21SSandeep Paulraj if (mmcstatus & MMCST0_RSPDNE) {
27057418d21SSandeep Paulraj /* Copy the response to the response buffer */
27157418d21SSandeep Paulraj if (cmd->resp_type & MMC_RSP_136) {
27257418d21SSandeep Paulraj cmd->response[0] = get_val(®s->mmcrsp67);
27357418d21SSandeep Paulraj cmd->response[1] = get_val(®s->mmcrsp45);
27457418d21SSandeep Paulraj cmd->response[2] = get_val(®s->mmcrsp23);
27557418d21SSandeep Paulraj cmd->response[3] = get_val(®s->mmcrsp01);
27657418d21SSandeep Paulraj } else if (cmd->resp_type & MMC_RSP_PRESENT) {
27757418d21SSandeep Paulraj cmd->response[0] = get_val(®s->mmcrsp67);
27857418d21SSandeep Paulraj }
27957418d21SSandeep Paulraj }
28057418d21SSandeep Paulraj
28157418d21SSandeep Paulraj if (data == NULL)
28257418d21SSandeep Paulraj return 0;
28357418d21SSandeep Paulraj
28457418d21SSandeep Paulraj if (data->flags == MMC_DATA_READ) {
28557418d21SSandeep Paulraj /* check for DATDNE along with DRRDY as the controller might
28657418d21SSandeep Paulraj * set the DATDNE without DRRDY for smaller transfers with
28757418d21SSandeep Paulraj * less than FIFO threshold bytes
28857418d21SSandeep Paulraj */
28957418d21SSandeep Paulraj status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
29057418d21SSandeep Paulraj status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
29157418d21SSandeep Paulraj data_buf = data->dest;
29257418d21SSandeep Paulraj } else {
29357418d21SSandeep Paulraj status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
29457418d21SSandeep Paulraj status_err = MMCST0_CRCWR;
29557418d21SSandeep Paulraj }
29657418d21SSandeep Paulraj
29757418d21SSandeep Paulraj /* Wait until all of the blocks are transferred */
29857418d21SSandeep Paulraj while (bytes_left) {
29957418d21SSandeep Paulraj err = dmmc_check_status(regs, &mmcstatus, status_rdy,
30057418d21SSandeep Paulraj status_err);
30157418d21SSandeep Paulraj if (err)
30257418d21SSandeep Paulraj return err;
30357418d21SSandeep Paulraj
30457418d21SSandeep Paulraj if (data->flags == MMC_DATA_READ) {
30557418d21SSandeep Paulraj /*
30657418d21SSandeep Paulraj * MMC controller sets the Data receive ready bit
30757418d21SSandeep Paulraj * (DRRDY) in MMCST0 even before the entire FIFO is
30857418d21SSandeep Paulraj * full. This results in erratic behavior if we start
30957418d21SSandeep Paulraj * reading the FIFO soon after DRRDY. Wait for the
31057418d21SSandeep Paulraj * FIFO full bit in MMCST1 for proper FIFO clearing.
31157418d21SSandeep Paulraj */
31257418d21SSandeep Paulraj if (bytes_left > fifo_bytes)
31357418d21SSandeep Paulraj dmmc_wait_fifo_status(regs, 0x4a);
3143ba36d60SDavide Bonfanti else if (bytes_left == fifo_bytes) {
31557418d21SSandeep Paulraj dmmc_wait_fifo_status(regs, 0x40);
3163ba36d60SDavide Bonfanti if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
3173ba36d60SDavide Bonfanti udelay(600);
3183ba36d60SDavide Bonfanti }
31957418d21SSandeep Paulraj
32057418d21SSandeep Paulraj for (i = 0; bytes_left && (i < fifo_words); i++) {
32157418d21SSandeep Paulraj cmddata = get_val(®s->mmcdrr);
32257418d21SSandeep Paulraj memcpy(data_buf, (char *)&cmddata, 4);
32357418d21SSandeep Paulraj data_buf += 4;
32457418d21SSandeep Paulraj bytes_left -= 4;
32557418d21SSandeep Paulraj }
32657418d21SSandeep Paulraj } else {
32757418d21SSandeep Paulraj /*
32857418d21SSandeep Paulraj * MMC controller sets the Data transmit ready bit
32957418d21SSandeep Paulraj * (DXRDY) in MMCST0 even before the entire FIFO is
33057418d21SSandeep Paulraj * empty. This results in erratic behavior if we start
33157418d21SSandeep Paulraj * writing the FIFO soon after DXRDY. Wait for the
33257418d21SSandeep Paulraj * FIFO empty bit in MMCST1 for proper FIFO clearing.
33357418d21SSandeep Paulraj */
33457418d21SSandeep Paulraj dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
33557418d21SSandeep Paulraj for (i = 0; bytes_left && (i < fifo_words); i++) {
33657418d21SSandeep Paulraj memcpy((char *)&cmddata, data_buf, 4);
33757418d21SSandeep Paulraj set_val(®s->mmcdxr, cmddata);
33857418d21SSandeep Paulraj data_buf += 4;
33957418d21SSandeep Paulraj bytes_left -= 4;
34057418d21SSandeep Paulraj }
34157418d21SSandeep Paulraj dmmc_busy_wait(regs);
34257418d21SSandeep Paulraj }
34357418d21SSandeep Paulraj }
34457418d21SSandeep Paulraj
34557418d21SSandeep Paulraj err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
34657418d21SSandeep Paulraj if (err)
34757418d21SSandeep Paulraj return err;
34857418d21SSandeep Paulraj
34957418d21SSandeep Paulraj return 0;
35057418d21SSandeep Paulraj }
35157418d21SSandeep Paulraj
35257418d21SSandeep Paulraj /* Initialize Davinci MMC controller */
353df6565c3SAdam Ford #if !CONFIG_IS_ENABLED(DM_MMC)
35457418d21SSandeep Paulraj static int dmmc_init(struct mmc *mmc)
35557418d21SSandeep Paulraj {
35657418d21SSandeep Paulraj struct davinci_mmc *host = mmc->priv;
357df6565c3SAdam Ford #else
358df6565c3SAdam Ford static int davinci_dm_mmc_init(struct udevice *dev)
359df6565c3SAdam Ford {
360df6565c3SAdam Ford struct davinci_mmc_priv *host = dev_get_priv(dev);
361df6565c3SAdam Ford #endif
36257418d21SSandeep Paulraj struct davinci_mmc_regs *regs = host->reg_base;
36357418d21SSandeep Paulraj
36457418d21SSandeep Paulraj /* Clear status registers explicitly - soft reset doesn't clear it
36557418d21SSandeep Paulraj * If Uboot is invoked from UBL with SDMMC Support, the status
36657418d21SSandeep Paulraj * registers can have uncleared bits
36757418d21SSandeep Paulraj */
36857418d21SSandeep Paulraj get_val(®s->mmcst0);
36957418d21SSandeep Paulraj get_val(®s->mmcst1);
37057418d21SSandeep Paulraj
37157418d21SSandeep Paulraj /* Hold software reset */
37257418d21SSandeep Paulraj set_bit(®s->mmcctl, MMCCTL_DATRST);
37357418d21SSandeep Paulraj set_bit(®s->mmcctl, MMCCTL_CMDRST);
37457418d21SSandeep Paulraj udelay(10);
37557418d21SSandeep Paulraj
37657418d21SSandeep Paulraj set_val(®s->mmcclk, 0x0);
37757418d21SSandeep Paulraj set_val(®s->mmctor, 0x1FFF);
37857418d21SSandeep Paulraj set_val(®s->mmctod, 0xFFFF);
37957418d21SSandeep Paulraj
38057418d21SSandeep Paulraj /* Clear software reset */
38157418d21SSandeep Paulraj clear_bit(®s->mmcctl, MMCCTL_DATRST);
38257418d21SSandeep Paulraj clear_bit(®s->mmcctl, MMCCTL_CMDRST);
38357418d21SSandeep Paulraj
38457418d21SSandeep Paulraj udelay(10);
38557418d21SSandeep Paulraj
38657418d21SSandeep Paulraj /* Reset FIFO - Always use the maximum fifo threshold */
38757418d21SSandeep Paulraj set_val(®s->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
38857418d21SSandeep Paulraj set_val(®s->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
38957418d21SSandeep Paulraj
39057418d21SSandeep Paulraj return 0;
39157418d21SSandeep Paulraj }
39257418d21SSandeep Paulraj
3934aa2ba3aSMasahiro Yamada /* Set buswidth or clock as indicated by the MMC framework */
394df6565c3SAdam Ford #if !CONFIG_IS_ENABLED(DM_MMC)
39507b0b9c0SJaehoon Chung static int dmmc_set_ios(struct mmc *mmc)
39657418d21SSandeep Paulraj {
39757418d21SSandeep Paulraj struct davinci_mmc *host = mmc->priv;
39857418d21SSandeep Paulraj struct davinci_mmc_regs *regs = host->reg_base;
399df6565c3SAdam Ford #else
400df6565c3SAdam Ford static int davinci_mmc_set_ios(struct udevice *dev)
401df6565c3SAdam Ford {
402df6565c3SAdam Ford struct mmc *mmc = mmc_get_mmc_dev(dev);
40357418d21SSandeep Paulraj
404df6565c3SAdam Ford struct davinci_mmc_priv *host = dev_get_priv(dev);
405df6565c3SAdam Ford struct davinci_mmc_regs *regs = host->reg_base;
406df6565c3SAdam Ford #endif
40757418d21SSandeep Paulraj /* Set the bus width */
40857418d21SSandeep Paulraj if (mmc->bus_width == 4)
40957418d21SSandeep Paulraj set_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
41057418d21SSandeep Paulraj else
41157418d21SSandeep Paulraj clear_bit(®s->mmcctl, MMCCTL_WIDTH_4_BIT);
41257418d21SSandeep Paulraj
41357418d21SSandeep Paulraj /* Set clock speed */
414df6565c3SAdam Ford if (mmc->clock) {
415df6565c3SAdam Ford #if !CONFIG_IS_ENABLED(DM_MMC)
41657418d21SSandeep Paulraj dmmc_set_clock(mmc, mmc->clock);
417df6565c3SAdam Ford #else
418df6565c3SAdam Ford davinci_mmc_set_clock(dev, mmc->clock);
419df6565c3SAdam Ford #endif
420df6565c3SAdam Ford }
42107b0b9c0SJaehoon Chung return 0;
42257418d21SSandeep Paulraj }
42357418d21SSandeep Paulraj
424df6565c3SAdam Ford #if !CONFIG_IS_ENABLED(DM_MMC)
425ab769f22SPantelis Antoniou static const struct mmc_ops dmmc_ops = {
426ab769f22SPantelis Antoniou .send_cmd = dmmc_send_cmd,
427ab769f22SPantelis Antoniou .set_ios = dmmc_set_ios,
428ab769f22SPantelis Antoniou .init = dmmc_init,
429ab769f22SPantelis Antoniou };
430df6565c3SAdam Ford #else
431*04355de7SAdam Ford
432*04355de7SAdam Ford static int davinci_mmc_getcd(struct udevice *dev)
433*04355de7SAdam Ford {
434*04355de7SAdam Ford int value = -1;
435*04355de7SAdam Ford #if CONFIG_IS_ENABLED(DM_GPIO)
436*04355de7SAdam Ford struct davinci_mmc_priv *priv = dev_get_priv(dev);
437*04355de7SAdam Ford value = dm_gpio_get_value(&priv->cd_gpio);
438*04355de7SAdam Ford #endif
439*04355de7SAdam Ford /* if no CD return as 1 */
440*04355de7SAdam Ford if (value < 0)
441*04355de7SAdam Ford return 1;
442*04355de7SAdam Ford
443*04355de7SAdam Ford return value;
444*04355de7SAdam Ford }
445*04355de7SAdam Ford
446*04355de7SAdam Ford static int davinci_mmc_getwp(struct udevice *dev)
447*04355de7SAdam Ford {
448*04355de7SAdam Ford int value = -1;
449*04355de7SAdam Ford #if CONFIG_IS_ENABLED(DM_GPIO)
450*04355de7SAdam Ford struct davinci_mmc_priv *priv = dev_get_priv(dev);
451*04355de7SAdam Ford
452*04355de7SAdam Ford value = dm_gpio_get_value(&priv->wp_gpio);
453*04355de7SAdam Ford #endif
454*04355de7SAdam Ford /* if no WP return as 0 */
455*04355de7SAdam Ford if (value < 0)
456*04355de7SAdam Ford return 0;
457*04355de7SAdam Ford
458*04355de7SAdam Ford return value;
459*04355de7SAdam Ford }
460*04355de7SAdam Ford
461df6565c3SAdam Ford static const struct dm_mmc_ops davinci_mmc_ops = {
462df6565c3SAdam Ford .send_cmd = davinci_mmc_send_cmd,
463df6565c3SAdam Ford .set_ios = davinci_mmc_set_ios,
464*04355de7SAdam Ford .get_cd = davinci_mmc_getcd,
465*04355de7SAdam Ford .get_wp = davinci_mmc_getwp,
466df6565c3SAdam Ford };
467df6565c3SAdam Ford #endif
468ab769f22SPantelis Antoniou
469df6565c3SAdam Ford #if !CONFIG_IS_ENABLED(DM_MMC)
47057418d21SSandeep Paulraj /* Called from board_mmc_init during startup. Can be called multiple times
47157418d21SSandeep Paulraj * depending on the number of slots available on board and controller
47257418d21SSandeep Paulraj */
47357418d21SSandeep Paulraj int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host)
47457418d21SSandeep Paulraj {
47593bfd616SPantelis Antoniou host->cfg.name = "davinci";
47693bfd616SPantelis Antoniou host->cfg.ops = &dmmc_ops;
47793bfd616SPantelis Antoniou host->cfg.f_min = 200000;
47893bfd616SPantelis Antoniou host->cfg.f_max = 25000000;
47993bfd616SPantelis Antoniou host->cfg.voltages = host->voltages;
48093bfd616SPantelis Antoniou host->cfg.host_caps = host->host_caps;
48157418d21SSandeep Paulraj
48293bfd616SPantelis Antoniou host->cfg.b_max = DAVINCI_MAX_BLOCKS;
48357418d21SSandeep Paulraj
48493bfd616SPantelis Antoniou mmc_create(&host->cfg, host);
48557418d21SSandeep Paulraj
48657418d21SSandeep Paulraj return 0;
48757418d21SSandeep Paulraj }
488df6565c3SAdam Ford #else
489df6565c3SAdam Ford
490df6565c3SAdam Ford
491df6565c3SAdam Ford static int davinci_mmc_probe(struct udevice *dev)
492df6565c3SAdam Ford {
493df6565c3SAdam Ford struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
494df6565c3SAdam Ford struct davinci_mmc_plat *plat = dev_get_platdata(dev);
495df6565c3SAdam Ford struct davinci_mmc_priv *priv = dev_get_priv(dev);
496df6565c3SAdam Ford struct mmc_config *cfg = &plat->cfg;
497df6565c3SAdam Ford struct davinci_of_data *data =
498df6565c3SAdam Ford (struct davinci_of_data *)dev_get_driver_data(dev);
499df6565c3SAdam Ford cfg->f_min = 200000;
500df6565c3SAdam Ford cfg->f_max = 25000000;
501df6565c3SAdam Ford cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
502df6565c3SAdam Ford cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
503df6565c3SAdam Ford cfg->b_max = DAVINCI_MAX_BLOCKS;
504df6565c3SAdam Ford
505df6565c3SAdam Ford if (data) {
506df6565c3SAdam Ford cfg->name = data->name;
507df6565c3SAdam Ford priv->version = data->version;
508df6565c3SAdam Ford }
509df6565c3SAdam Ford
510df6565c3SAdam Ford priv->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
511df6565c3SAdam Ford priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
512df6565c3SAdam Ford
513*04355de7SAdam Ford #if CONFIG_IS_ENABLED(DM_GPIO)
514*04355de7SAdam Ford /* These GPIOs are optional */
515*04355de7SAdam Ford gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
516*04355de7SAdam Ford gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
517*04355de7SAdam Ford #endif
518*04355de7SAdam Ford
519df6565c3SAdam Ford upriv->mmc = &plat->mmc;
520df6565c3SAdam Ford
521df6565c3SAdam Ford return davinci_dm_mmc_init(dev);
522df6565c3SAdam Ford }
523df6565c3SAdam Ford
524df6565c3SAdam Ford static int davinci_mmc_bind(struct udevice *dev)
525df6565c3SAdam Ford {
526df6565c3SAdam Ford struct davinci_mmc_plat *plat = dev_get_platdata(dev);
527df6565c3SAdam Ford
528df6565c3SAdam Ford return mmc_bind(dev, &plat->mmc, &plat->cfg);
529df6565c3SAdam Ford }
530df6565c3SAdam Ford
531df6565c3SAdam Ford
532df6565c3SAdam Ford const struct davinci_of_data davinci_mmc_host_info[] = {
533df6565c3SAdam Ford {
534df6565c3SAdam Ford .name = "dm6441-mmc",
535df6565c3SAdam Ford .version = MMC_CTLR_VERSION_1,
536df6565c3SAdam Ford },
537df6565c3SAdam Ford {
538df6565c3SAdam Ford .name = "da830-mmc",
539df6565c3SAdam Ford .version = MMC_CTLR_VERSION_2,
540df6565c3SAdam Ford },
541df6565c3SAdam Ford {},
542df6565c3SAdam Ford };
543df6565c3SAdam Ford
544df6565c3SAdam Ford static const struct udevice_id davinci_mmc_ids[] = {
545df6565c3SAdam Ford {
546df6565c3SAdam Ford .compatible = "ti,dm6441-mmc",
547df6565c3SAdam Ford .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_1]
548df6565c3SAdam Ford },
549df6565c3SAdam Ford {
550df6565c3SAdam Ford .compatible = "ti,da830-mmc",
551df6565c3SAdam Ford .data = (ulong) &davinci_mmc_host_info[MMC_CTLR_VERSION_2]
552df6565c3SAdam Ford },
553df6565c3SAdam Ford {},
554df6565c3SAdam Ford };
555df6565c3SAdam Ford
556df6565c3SAdam Ford U_BOOT_DRIVER(davinci_mmc_drv) = {
557df6565c3SAdam Ford .name = "davinci_mmc",
558df6565c3SAdam Ford .id = UCLASS_MMC,
559df6565c3SAdam Ford .of_match = davinci_mmc_ids,
560df6565c3SAdam Ford #if CONFIG_BLK
561df6565c3SAdam Ford .bind = davinci_mmc_bind,
562df6565c3SAdam Ford #endif
563df6565c3SAdam Ford .probe = davinci_mmc_probe,
564df6565c3SAdam Ford .ops = &davinci_mmc_ops,
565df6565c3SAdam Ford .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
566df6565c3SAdam Ford .priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
567df6565c3SAdam Ford };
568df6565c3SAdam Ford #endif
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