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Searched refs:phy_addr (Results 1 – 25 of 90) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-davinci/
H A Ddp83848.c21 int dp83848_is_phy_connected(int phy_addr) in dp83848_is_phy_connected() argument
25 if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID1_REG, &id1)) in dp83848_is_phy_connected()
27 if (!davinci_eth_phy_read(phy_addr, DP83848_PHYID2_REG, &id2)) in dp83848_is_phy_connected()
36 int dp83848_get_link_speed(int phy_addr) in dp83848_get_link_speed() argument
41 if (!davinci_eth_phy_read(phy_addr, DP83848_STAT_REG, &tmp)) in dp83848_get_link_speed()
47 if (!davinci_eth_phy_read(phy_addr, DP83848_PHY_STAT_REG, &tmp)) in dp83848_get_link_speed()
64 int dp83848_init_phy(int phy_addr) in dp83848_init_phy() argument
68 if (!dp83848_get_link_speed(phy_addr)) { in dp83848_init_phy()
71 ret = dp83848_get_link_speed(phy_addr); in dp83848_init_phy()
75 davinci_eth_phy_write(phy_addr, DP83848_PHY_INTR_CTRL_REG, 0); in dp83848_init_phy()
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H A Dlxt972.c22 int lxt972_is_phy_connected(int phy_addr) in lxt972_is_phy_connected() argument
26 if (!davinci_eth_phy_read(phy_addr, MII_PHYSID1, &id1)) in lxt972_is_phy_connected()
28 if (!davinci_eth_phy_read(phy_addr, MII_PHYSID2, &id2)) in lxt972_is_phy_connected()
37 int lxt972_get_link_speed(int phy_addr) in lxt972_get_link_speed() argument
42 if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_STAT2, &stat1)) in lxt972_get_link_speed()
48 if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) in lxt972_get_link_speed()
53 davinci_eth_phy_write(phy_addr, PHY_LXT971_DIG_CFG, tmp); in lxt972_get_link_speed()
55 if (!davinci_eth_phy_read(phy_addr, PHY_LXT971_DIG_CFG, &tmp)) in lxt972_get_link_speed()
72 int lxt972_init_phy(int phy_addr) in lxt972_init_phy() argument
76 if (!lxt972_get_link_speed(phy_addr)) { in lxt972_init_phy()
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H A Dksz8873.c24 int ksz8873_is_phy_connected(int phy_addr) in ksz8873_is_phy_connected() argument
28 return davinci_eth_phy_read(phy_addr, MII_PHYSID1, &dummy); in ksz8873_is_phy_connected()
31 int ksz8873_get_link_speed(int phy_addr) in ksz8873_get_link_speed() argument
43 int ksz8873_init_phy(int phy_addr) in ksz8873_init_phy() argument
49 int ksz8873_auto_negotiate(int phy_addr) in ksz8873_auto_negotiate() argument
51 return dp83848_get_link_speed(phy_addr); in ksz8873_auto_negotiate()
H A Det1011c.c25 int et1011c_get_link_speed(int phy_addr) in et1011c_get_link_speed() argument
29 if (davinci_eth_phy_read(phy_addr, MII_STATUS_REG, &data) && (data & 0x04)) { in et1011c_get_link_speed()
30 davinci_eth_phy_read(phy_addr, MII_PHY_CONFIG_REG, &data); in et1011c_get_link_speed()
32 davinci_eth_phy_write(phy_addr, MII_PHY_CONFIG_REG, in et1011c_get_link_speed()
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Demac_defs.h73 int ksz8873_is_phy_connected(int phy_addr);
74 int ksz8873_get_link_speed(int phy_addr);
75 int ksz8873_init_phy(int phy_addr);
76 int ksz8873_auto_negotiate(int phy_addr);
79 int lxt972_is_phy_connected(int phy_addr);
80 int lxt972_get_link_speed(int phy_addr);
81 int lxt972_init_phy(int phy_addr);
82 int lxt972_auto_negotiate(int phy_addr);
85 int dp83848_is_phy_connected(int phy_addr);
86 int dp83848_get_link_speed(int phy_addr);
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/openbmc/u-boot/drivers/net/phy/
H A Dmv88e6352.c32 static int sw_wait_rdy(const char *devname, u8 phy_addr) in sw_wait_rdy() argument
41 ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command); in sw_wait_rdy()
56 static int sw_reg_read(const char *devname, u8 phy_addr, u8 port, in sw_reg_read() argument
62 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_read()
69 ret = miiphy_write(devname, phy_addr, COMMAND_REG, command); in sw_reg_read()
73 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_read()
77 ret = miiphy_read(devname, phy_addr, DATA_REG, data); in sw_reg_read()
82 static int sw_reg_write(const char *devname, u8 phy_addr, u8 port, in sw_reg_write() argument
88 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_write()
93 ret = miiphy_write(devname, phy_addr, DATA_REG, data); in sw_reg_write()
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/openbmc/u-boot/board/freescale/t104xrdb/
H A Deth.c23 int phy_addr = 0; in board_eth_init() local
70 phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; in board_eth_init()
72 phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; in board_eth_init()
74 phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; in board_eth_init()
75 fm_info_set_phy_address(i, phy_addr); in board_eth_init()
80 phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; in board_eth_init()
82 phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; in board_eth_init()
83 fm_info_set_phy_address(i, phy_addr); in board_eth_init()
111 phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; in board_eth_init()
115 vsc9953_port_info_set_phy_address(i, phy_addr); in board_eth_init()
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/openbmc/u-boot/drivers/net/ti/
H A Ddavinci_emac.c60 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) argument
62 #define emac_gigabit_enable(phy_addr) /* no gigabit to enable */ argument
72 static int gen_init_phy(int phy_addr);
73 static int gen_is_phy_connected(int phy_addr);
74 static int gen_get_link_speed(int phy_addr);
75 static int gen_auto_negotiate(int phy_addr);
206 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data) in davinci_eth_phy_read() argument
216 ((phy_addr & 0x1f) << 16), in davinci_eth_phy_read()
232 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data) in davinci_eth_phy_write() argument
241 ((phy_addr & 0x1f) << 16) | in davinci_eth_phy_write()
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H A Ddavinci_emac.h293 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
294 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
298 int (*init)(int phy_addr);
299 int (*is_phy_connected)(int phy_addr);
300 int (*get_link_speed)(int phy_addr);
301 int (*auto_negotiate)(int phy_addr);
/openbmc/u-boot/board/freescale/ls1088a/
H A Deth_ls1088aqds.c92 int phy_addr = 0; in sgmii_configure_repeater() local
105 phy_addr = 4; in sgmii_configure_repeater()
109 phy_addr = 0; in sgmii_configure_repeater()
113 phy_addr = 0xc; in sgmii_configure_repeater()
117 phy_addr = 8; in sgmii_configure_repeater()
129 ret = miiphy_write(dev, phy_addr, 0x1f, 3); in sgmii_configure_repeater()
134 ret = miiphy_read(dev, phy_addr, 0x11, &value); in sgmii_configure_repeater()
141 miiphy_write(dev, phy_addr, 0x1f, 0); in sgmii_configure_repeater()
172 ret = miiphy_read(dev, phy_addr, 0x11, &value); in sgmii_configure_repeater()
177 ret = miiphy_read(dev, phy_addr, 0x11, &value); in sgmii_configure_repeater()
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/openbmc/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c16 static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_write_addr() argument
26 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_write_addr()
50 static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_phy_read() argument
64 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_read()
69 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_phy_read()
100 phy_addr, reg_addr, val); in pfe_phy_read()
105 static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_phy_write() argument
119 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_write()
124 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_phy_write()
150 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr, in pfe_phy_write()
/openbmc/u-boot/drivers/net/
H A Daspeed_mdio.c58 extern int aspeed_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, in aspeed_mdio_read() argument
67 FTGMAC100_PHYCR_NEW_PHYAD(phy_addr) | in aspeed_mdio_read()
115 extern int aspeed_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, in aspeed_mdio_write() argument
130 phycr = FTGMAC100_PHYCR_PHYAD(phy_addr) in aspeed_mdio_write()
144 "phy_addr: %x\n", phy_addr); in aspeed_mdio_write()
155 FTGMAC100_PHYCR_NEW_PHYAD(phy_addr) | in aspeed_mdio_write()
166 "phy_addr: %x\n", phy_addr); in aspeed_mdio_write()
H A Ddnet.c31 unsigned short phy_addr; member
75 dnet->phy_addr, reg, value); in dnet_mdio_write()
88 tmp |= (dnet->phy_addr << 8); in dnet_mdio_write()
114 value = (dnet->phy_addr << 8); in dnet_mdio_read()
128 dnet->phy_addr, reg, value); in dnet_mdio_read()
251 dnet->phy_addr = i; in dnet_phy_init()
359 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr) in dnet_eth_initialize() argument
375 dnet->phy_addr = phy_addr; in dnet_eth_initialize()
H A Dmcfmii.c142 return info->phy_addr; in mii_discover_phy()
236 info->phy_addr = mii_discover_phy(dev); in __mii_init()
242 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); in __mii_init()
253 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); in __mii_init()
264 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; in __mii_init()
265 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); in __mii_init()
H A Duli526x.c136 u8 phy_addr; member
346 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id); in uli526x_disable()
378 db->phy_addr = 1; in uli526x_init()
384 db->phy_addr = phy_tmp; in uli526x_init()
391 printf("%s(): db->phy_addr= 0x%x\n", __FUNCTION__, db->phy_addr); in uli526x_init()
402 db->phy_addr, 0, db->chip_id); in uli526x_init()
404 uli_phy_write(db->ioaddr, db->phy_addr, 0, in uli526x_init()
779 db->phy_addr, 4, db->chip_id) & ~0x01e0; in uli526x_set_phyxcer()
800 uli_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id); in uli526x_set_phyxcer()
803 uli_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id); in uli526x_set_phyxcer()
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H A Daspeed_mdio.h11 extern int aspeed_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
13 extern int aspeed_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
H A Dftgmac100.c83 u32 phy_addr; member
100 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, in ftgmac100_mdio_read() argument
110 FTGMAC100_PHYCR_PHYAD(phy_addr) | in ftgmac100_mdio_read()
120 bus->name, phy_addr, reg_addr); in ftgmac100_mdio_read()
129 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, in ftgmac100_mdio_write() argument
139 FTGMAC100_PHYCR_PHYAD(phy_addr) | in ftgmac100_mdio_write()
152 bus->name, phy_addr, reg_addr); in ftgmac100_mdio_write()
227 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); in ftgmac100_phy_init()
556 priv->phy_addr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); in ftgmac100_ofdata_to_platdata()
558 priv->phy_addr = 0; in ftgmac100_ofdata_to_platdata()
/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c174 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
179 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up()
184 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0); in comphy_pcie_power_up()
189 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
194 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF); in comphy_pcie_power_up()
199 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up()
213 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
222 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate, in comphy_pcie_power_up()
229 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
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/openbmc/u-boot/board/freescale/t1040qds/
H A Deth.c444 int phy_addr; in board_eth_init() local
505 phy_addr = 0; in board_eth_init()
515 phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + in board_eth_init()
528 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR in board_eth_init()
531 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR; in board_eth_init()
541 phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + in board_eth_init()
550 phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR in board_eth_init()
581 vsc9953_port_info_set_phy_address(i, phy_addr); in board_eth_init()
/openbmc/u-boot/drivers/net/ldpaa_eth/
H A Dldpaa_wriop.c39 dpmac_info[dpmac_id].phy_addr[phy_num] = -1; in wriop_init_dpmac()
52 dpmac_info[dpmac_id].phy_addr[phy_num] = -1; in wriop_init_dpmac_enet_if()
138 dpmac_info[i].phy_addr[phy_num] = address; in wriop_set_phy_address()
152 return dpmac_info[i].phy_addr[phy_num]; in wriop_get_phy_address()
/openbmc/u-boot/board/ti/am335x/
H A Dboard.c637 int phy_addr; in ft_board_setup() local
662 phy_addr = cpsw_get_slave_phy_addr(ethdev, i); in ft_board_setup()
668 if (phy_id[1] != phy_addr) { in ft_board_setup()
670 alias, phy_id[1], phy_addr); in ft_board_setup()
673 phy_id[1] = cpu_to_fdt32(phy_addr); in ft_board_setup()
687 if (ret != phy_addr) { in ft_board_setup()
689 alias, ret, phy_addr); in ft_board_setup()
692 cpu_to_fdt32(phy_addr)); in ft_board_setup()
893 .phy_addr = 0,
898 .phy_addr = 1,
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/openbmc/u-boot/include/
H A Dmv88e6352.h71 int mv88e_sw_reset(const char *devname, u8 phy_addr);
72 int mv88e_sw_program(const char *devname, u8 phy_addr,
H A Dnetdev.h37 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
52 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
56 int mvneta_initialize(bd_t *bis, int base_addr, int devnum, int phy_addr);
/openbmc/qemu/hw/misc/macio/
H A Dmac_dbdma.c81 DBDMA_DPRINTFCH(ch, " phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr)); in dump_dbdma_cmd()
453 uint32_t phy_addr; in channel_run() local
476 phy_addr = le32_to_cpu(current->phy_addr); in channel_run()
487 start_output(ch, key, phy_addr, req_count, 0); in channel_run()
492 start_output(ch, key, phy_addr, req_count, 1); in channel_run()
497 start_input(ch, key, phy_addr, req_count, 0); in channel_run()
502 start_input(ch, key, phy_addr, req_count, 1); in channel_run()
518 phy_addr &= ~3; in channel_run()
521 phy_addr &= ~1; in channel_run()
528 load_word(ch, key, phy_addr, req_count); in channel_run()
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/openbmc/u-boot/board/freescale/ls2080aqds/
H A Deth.c221 int phy_addr = 0; in qsgmii_configure_repeater() local
242 phy_addr = 0; in qsgmii_configure_repeater()
250 phy_addr = 4; in qsgmii_configure_repeater()
258 phy_addr = 8; in qsgmii_configure_repeater()
266 phy_addr = 0xc; in qsgmii_configure_repeater()
272 ret = miiphy_write(dev, phy_addr, 0x1f, 3); in qsgmii_configure_repeater()
274 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
276 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
305 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
309 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()

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