183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
244937214SPrabhakar Kushwaha /*
344937214SPrabhakar Kushwaha * Copyright 2015 Freescale Semiconductor, Inc.
444937214SPrabhakar Kushwaha */
544937214SPrabhakar Kushwaha
644937214SPrabhakar Kushwaha #include <common.h>
744937214SPrabhakar Kushwaha #include <netdev.h>
844937214SPrabhakar Kushwaha #include <asm/io.h>
944937214SPrabhakar Kushwaha #include <asm/arch/fsl_serdes.h>
1044937214SPrabhakar Kushwaha #include <hwconfig.h>
1144937214SPrabhakar Kushwaha #include <fsl_mdio.h>
1244937214SPrabhakar Kushwaha #include <malloc.h>
1344937214SPrabhakar Kushwaha #include <fm_eth.h>
1444937214SPrabhakar Kushwaha #include <i2c.h>
1544937214SPrabhakar Kushwaha #include <miiphy.h>
1633a8991aSBogdan Purcareata #include <fsl-mc/fsl_mc.h>
1744937214SPrabhakar Kushwaha #include <fsl-mc/ldpaa_wriop.h>
1844937214SPrabhakar Kushwaha
1944937214SPrabhakar Kushwaha #include "../common/qixis.h"
2044937214SPrabhakar Kushwaha
2144937214SPrabhakar Kushwaha #include "ls2080aqds_qixis.h"
2244937214SPrabhakar Kushwaha
2330677deeSPratiyush Mohan Srivastava #define MC_BOOT_ENV_VAR "mcinitcmd"
2444937214SPrabhakar Kushwaha
251f55a938SSantan Kumar #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
2644937214SPrabhakar Kushwaha /* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
2744937214SPrabhakar Kushwaha * Bank 1 -> Lanes A, B, C, D, E, F, G, H
2844937214SPrabhakar Kushwaha * Bank 2 -> Lanes A,B, C, D, E, F, G, H
2944937214SPrabhakar Kushwaha */
3044937214SPrabhakar Kushwaha
3144937214SPrabhakar Kushwaha /* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
3244937214SPrabhakar Kushwaha * means that the mapping must be determined dynamically, or that the lane
3344937214SPrabhakar Kushwaha * maps to something other than a board slot.
3444937214SPrabhakar Kushwaha */
3544937214SPrabhakar Kushwaha
3644937214SPrabhakar Kushwaha static u8 lane_to_slot_fsm1[] = {
3744937214SPrabhakar Kushwaha 0, 0, 0, 0, 0, 0, 0, 0
3844937214SPrabhakar Kushwaha };
3944937214SPrabhakar Kushwaha
4044937214SPrabhakar Kushwaha static u8 lane_to_slot_fsm2[] = {
4144937214SPrabhakar Kushwaha 0, 0, 0, 0, 0, 0, 0, 0
4244937214SPrabhakar Kushwaha };
4344937214SPrabhakar Kushwaha
4444937214SPrabhakar Kushwaha /* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
4544937214SPrabhakar Kushwaha * housed.
4644937214SPrabhakar Kushwaha */
4744937214SPrabhakar Kushwaha
4844937214SPrabhakar Kushwaha static int xqsgii_riser_phy_addr[] = {
4944937214SPrabhakar Kushwaha XQSGMII_CARD_PHY1_PORT0_ADDR,
5044937214SPrabhakar Kushwaha XQSGMII_CARD_PHY2_PORT0_ADDR,
5144937214SPrabhakar Kushwaha XQSGMII_CARD_PHY3_PORT0_ADDR,
5244937214SPrabhakar Kushwaha XQSGMII_CARD_PHY4_PORT0_ADDR,
5344937214SPrabhakar Kushwaha XQSGMII_CARD_PHY3_PORT2_ADDR,
5444937214SPrabhakar Kushwaha XQSGMII_CARD_PHY1_PORT2_ADDR,
5544937214SPrabhakar Kushwaha XQSGMII_CARD_PHY4_PORT2_ADDR,
5644937214SPrabhakar Kushwaha XQSGMII_CARD_PHY2_PORT2_ADDR,
5744937214SPrabhakar Kushwaha };
5844937214SPrabhakar Kushwaha
5944937214SPrabhakar Kushwaha static int sgmii_riser_phy_addr[] = {
6044937214SPrabhakar Kushwaha SGMII_CARD_PORT1_PHY_ADDR,
6144937214SPrabhakar Kushwaha SGMII_CARD_PORT2_PHY_ADDR,
6244937214SPrabhakar Kushwaha SGMII_CARD_PORT3_PHY_ADDR,
6344937214SPrabhakar Kushwaha SGMII_CARD_PORT4_PHY_ADDR,
6444937214SPrabhakar Kushwaha };
6544937214SPrabhakar Kushwaha
6644937214SPrabhakar Kushwaha /* Slot2 does not have EMI connections */
67fc35addeSPriyanka Jain #define EMI_NONE 0xFF
6844937214SPrabhakar Kushwaha #define EMI1_SLOT1 0
6944937214SPrabhakar Kushwaha #define EMI1_SLOT2 1
7044937214SPrabhakar Kushwaha #define EMI1_SLOT3 2
7144937214SPrabhakar Kushwaha #define EMI1_SLOT4 3
7244937214SPrabhakar Kushwaha #define EMI1_SLOT5 4
7344937214SPrabhakar Kushwaha #define EMI1_SLOT6 5
7444937214SPrabhakar Kushwaha #define EMI2 6
7544937214SPrabhakar Kushwaha #define SFP_TX 0
7644937214SPrabhakar Kushwaha
7744937214SPrabhakar Kushwaha static const char * const mdio_names[] = {
7844937214SPrabhakar Kushwaha "LS2080A_QDS_MDIO0",
7944937214SPrabhakar Kushwaha "LS2080A_QDS_MDIO1",
8044937214SPrabhakar Kushwaha "LS2080A_QDS_MDIO2",
8144937214SPrabhakar Kushwaha "LS2080A_QDS_MDIO3",
8244937214SPrabhakar Kushwaha "LS2080A_QDS_MDIO4",
8344937214SPrabhakar Kushwaha "LS2080A_QDS_MDIO5",
8444937214SPrabhakar Kushwaha DEFAULT_WRIOP_MDIO2_NAME,
8544937214SPrabhakar Kushwaha };
8644937214SPrabhakar Kushwaha
8744937214SPrabhakar Kushwaha struct ls2080a_qds_mdio {
8844937214SPrabhakar Kushwaha u8 muxval;
8944937214SPrabhakar Kushwaha struct mii_dev *realbus;
9044937214SPrabhakar Kushwaha };
9144937214SPrabhakar Kushwaha
sgmii_configure_repeater(int serdes_port)9244937214SPrabhakar Kushwaha static void sgmii_configure_repeater(int serdes_port)
9344937214SPrabhakar Kushwaha {
9444937214SPrabhakar Kushwaha struct mii_dev *bus;
9544937214SPrabhakar Kushwaha uint8_t a = 0xf;
9644937214SPrabhakar Kushwaha int i, j, ret;
9744937214SPrabhakar Kushwaha int dpmac_id = 0, dpmac, mii_bus = 0;
9844937214SPrabhakar Kushwaha unsigned short value;
9944937214SPrabhakar Kushwaha char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
10044937214SPrabhakar Kushwaha uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
10144937214SPrabhakar Kushwaha
10244937214SPrabhakar Kushwaha uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
10344937214SPrabhakar Kushwaha uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
10444937214SPrabhakar Kushwaha uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
10544937214SPrabhakar Kushwaha uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
10644937214SPrabhakar Kushwaha
10744937214SPrabhakar Kushwaha int *riser_phy_addr = &xqsgii_riser_phy_addr[0];
10844937214SPrabhakar Kushwaha
10944937214SPrabhakar Kushwaha /* Set I2c to Slot 1 */
11044937214SPrabhakar Kushwaha i2c_write(0x77, 0, 0, &a, 1);
11144937214SPrabhakar Kushwaha
11244937214SPrabhakar Kushwaha for (dpmac = 0; dpmac < 8; dpmac++) {
11344937214SPrabhakar Kushwaha /* Check the PHY status */
11444937214SPrabhakar Kushwaha switch (serdes_port) {
11544937214SPrabhakar Kushwaha case 1:
11644937214SPrabhakar Kushwaha mii_bus = 0;
11744937214SPrabhakar Kushwaha dpmac_id = dpmac + 1;
11844937214SPrabhakar Kushwaha break;
11944937214SPrabhakar Kushwaha case 2:
12044937214SPrabhakar Kushwaha mii_bus = 1;
12144937214SPrabhakar Kushwaha dpmac_id = dpmac + 9;
12244937214SPrabhakar Kushwaha a = 0xb;
12344937214SPrabhakar Kushwaha i2c_write(0x76, 0, 0, &a, 1);
12444937214SPrabhakar Kushwaha break;
12544937214SPrabhakar Kushwaha }
12644937214SPrabhakar Kushwaha
12744937214SPrabhakar Kushwaha ret = miiphy_set_current_dev(dev[mii_bus]);
12844937214SPrabhakar Kushwaha if (ret > 0)
12944937214SPrabhakar Kushwaha goto error;
13044937214SPrabhakar Kushwaha
13144937214SPrabhakar Kushwaha bus = mdio_get_current_dev();
13244937214SPrabhakar Kushwaha debug("Reading from bus %s\n", bus->name);
13344937214SPrabhakar Kushwaha
13444937214SPrabhakar Kushwaha ret = miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f,
13544937214SPrabhakar Kushwaha 3);
13644937214SPrabhakar Kushwaha if (ret > 0)
13744937214SPrabhakar Kushwaha goto error;
13844937214SPrabhakar Kushwaha
13944937214SPrabhakar Kushwaha mdelay(10);
14044937214SPrabhakar Kushwaha ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11,
14144937214SPrabhakar Kushwaha &value);
14244937214SPrabhakar Kushwaha if (ret > 0)
14344937214SPrabhakar Kushwaha goto error;
14444937214SPrabhakar Kushwaha
14544937214SPrabhakar Kushwaha mdelay(10);
14644937214SPrabhakar Kushwaha
147c435a7c8SShaohui Xie if ((value & 0xfff) == 0x401) {
14844937214SPrabhakar Kushwaha printf("DPMAC %d:PHY is ..... Configured\n", dpmac_id);
149c435a7c8SShaohui Xie miiphy_write(dev[mii_bus], riser_phy_addr[dpmac],
150c435a7c8SShaohui Xie 0x1f, 0);
15144937214SPrabhakar Kushwaha continue;
15244937214SPrabhakar Kushwaha }
15344937214SPrabhakar Kushwaha
15444937214SPrabhakar Kushwaha for (i = 0; i < 4; i++) {
15544937214SPrabhakar Kushwaha for (j = 0; j < 4; j++) {
15644937214SPrabhakar Kushwaha a = 0x18;
15744937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 6, 1, &a, 1);
15844937214SPrabhakar Kushwaha a = 0x38;
15944937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
16044937214SPrabhakar Kushwaha a = 0x4;
16144937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 8, 1, &a, 1);
16244937214SPrabhakar Kushwaha
16344937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 0xf, 1,
16444937214SPrabhakar Kushwaha &ch_a_eq[i], 1);
16544937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 0x11, 1,
16644937214SPrabhakar Kushwaha &ch_a_ctl2[j], 1);
16744937214SPrabhakar Kushwaha
16844937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 0x16, 1,
16944937214SPrabhakar Kushwaha &ch_b_eq[i], 1);
17044937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 0x18, 1,
17144937214SPrabhakar Kushwaha &ch_b_ctl2[j], 1);
17244937214SPrabhakar Kushwaha
17344937214SPrabhakar Kushwaha a = 0x14;
17444937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);
17544937214SPrabhakar Kushwaha a = 0xb5;
17644937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);
17744937214SPrabhakar Kushwaha a = 0x20;
17844937214SPrabhakar Kushwaha i2c_write(i2c_addr[dpmac], 4, 1, &a, 1);
17944937214SPrabhakar Kushwaha mdelay(100);
18044937214SPrabhakar Kushwaha ret = miiphy_read(dev[mii_bus],
18144937214SPrabhakar Kushwaha riser_phy_addr[dpmac],
18244937214SPrabhakar Kushwaha 0x11, &value);
18344937214SPrabhakar Kushwaha if (ret > 0)
18444937214SPrabhakar Kushwaha goto error;
18544937214SPrabhakar Kushwaha
186c435a7c8SShaohui Xie mdelay(100);
18744937214SPrabhakar Kushwaha ret = miiphy_read(dev[mii_bus],
18844937214SPrabhakar Kushwaha riser_phy_addr[dpmac],
18944937214SPrabhakar Kushwaha 0x11, &value);
19044937214SPrabhakar Kushwaha if (ret > 0)
19144937214SPrabhakar Kushwaha goto error;
19244937214SPrabhakar Kushwaha
193c435a7c8SShaohui Xie if ((value & 0xfff) == 0x401) {
19444937214SPrabhakar Kushwaha printf("DPMAC %d :PHY is configured ",
19544937214SPrabhakar Kushwaha dpmac_id);
19644937214SPrabhakar Kushwaha printf("after setting repeater 0x%x\n",
19744937214SPrabhakar Kushwaha value);
19844937214SPrabhakar Kushwaha i = 5;
19944937214SPrabhakar Kushwaha j = 5;
200c435a7c8SShaohui Xie } else {
20144937214SPrabhakar Kushwaha printf("DPMAC %d :PHY is failed to ",
20244937214SPrabhakar Kushwaha dpmac_id);
20344937214SPrabhakar Kushwaha printf("configure the repeater 0x%x\n",
20444937214SPrabhakar Kushwaha value);
20544937214SPrabhakar Kushwaha }
20644937214SPrabhakar Kushwaha }
20744937214SPrabhakar Kushwaha }
208c435a7c8SShaohui Xie miiphy_write(dev[mii_bus], riser_phy_addr[dpmac], 0x1f, 0);
209c435a7c8SShaohui Xie }
21044937214SPrabhakar Kushwaha error:
21144937214SPrabhakar Kushwaha if (ret)
21244937214SPrabhakar Kushwaha printf("DPMAC %d ..... FAILED to configure PHY\n", dpmac_id);
21344937214SPrabhakar Kushwaha return;
21444937214SPrabhakar Kushwaha }
21544937214SPrabhakar Kushwaha
qsgmii_configure_repeater(int dpmac)21644937214SPrabhakar Kushwaha static void qsgmii_configure_repeater(int dpmac)
21744937214SPrabhakar Kushwaha {
21844937214SPrabhakar Kushwaha uint8_t a = 0xf;
21944937214SPrabhakar Kushwaha int i, j;
22044937214SPrabhakar Kushwaha int i2c_phy_addr = 0;
22144937214SPrabhakar Kushwaha int phy_addr = 0;
22244937214SPrabhakar Kushwaha int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
22344937214SPrabhakar Kushwaha
22444937214SPrabhakar Kushwaha uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
22544937214SPrabhakar Kushwaha uint8_t ch_a_ctl2[] = {0x81, 0x82, 0x83, 0x84};
22644937214SPrabhakar Kushwaha uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
22744937214SPrabhakar Kushwaha uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
22844937214SPrabhakar Kushwaha
22944937214SPrabhakar Kushwaha const char *dev = "LS2080A_QDS_MDIO0";
23044937214SPrabhakar Kushwaha int ret = 0;
23144937214SPrabhakar Kushwaha unsigned short value;
23244937214SPrabhakar Kushwaha
23344937214SPrabhakar Kushwaha /* Set I2c to Slot 1 */
23444937214SPrabhakar Kushwaha i2c_write(0x77, 0, 0, &a, 1);
23544937214SPrabhakar Kushwaha
23644937214SPrabhakar Kushwaha switch (dpmac) {
23744937214SPrabhakar Kushwaha case 1:
23844937214SPrabhakar Kushwaha case 2:
23944937214SPrabhakar Kushwaha case 3:
24044937214SPrabhakar Kushwaha case 4:
24144937214SPrabhakar Kushwaha i2c_phy_addr = i2c_addr[0];
24244937214SPrabhakar Kushwaha phy_addr = 0;
24344937214SPrabhakar Kushwaha break;
24444937214SPrabhakar Kushwaha
24544937214SPrabhakar Kushwaha case 5:
24644937214SPrabhakar Kushwaha case 6:
24744937214SPrabhakar Kushwaha case 7:
24844937214SPrabhakar Kushwaha case 8:
24944937214SPrabhakar Kushwaha i2c_phy_addr = i2c_addr[1];
25044937214SPrabhakar Kushwaha phy_addr = 4;
25144937214SPrabhakar Kushwaha break;
25244937214SPrabhakar Kushwaha
25344937214SPrabhakar Kushwaha case 9:
25444937214SPrabhakar Kushwaha case 10:
25544937214SPrabhakar Kushwaha case 11:
25644937214SPrabhakar Kushwaha case 12:
25744937214SPrabhakar Kushwaha i2c_phy_addr = i2c_addr[2];
25844937214SPrabhakar Kushwaha phy_addr = 8;
25944937214SPrabhakar Kushwaha break;
26044937214SPrabhakar Kushwaha
26144937214SPrabhakar Kushwaha case 13:
26244937214SPrabhakar Kushwaha case 14:
26344937214SPrabhakar Kushwaha case 15:
26444937214SPrabhakar Kushwaha case 16:
26544937214SPrabhakar Kushwaha i2c_phy_addr = i2c_addr[3];
26644937214SPrabhakar Kushwaha phy_addr = 0xc;
26744937214SPrabhakar Kushwaha break;
26844937214SPrabhakar Kushwaha }
26944937214SPrabhakar Kushwaha
27044937214SPrabhakar Kushwaha /* Check the PHY status */
27144937214SPrabhakar Kushwaha ret = miiphy_set_current_dev(dev);
27244937214SPrabhakar Kushwaha ret = miiphy_write(dev, phy_addr, 0x1f, 3);
27344937214SPrabhakar Kushwaha mdelay(10);
27444937214SPrabhakar Kushwaha ret = miiphy_read(dev, phy_addr, 0x11, &value);
27544937214SPrabhakar Kushwaha mdelay(10);
27644937214SPrabhakar Kushwaha ret = miiphy_read(dev, phy_addr, 0x11, &value);
27744937214SPrabhakar Kushwaha mdelay(10);
27844937214SPrabhakar Kushwaha if ((value & 0xf) == 0xf) {
27944937214SPrabhakar Kushwaha printf("DPMAC %d :PHY is ..... Configured\n", dpmac);
28044937214SPrabhakar Kushwaha return;
28144937214SPrabhakar Kushwaha }
28244937214SPrabhakar Kushwaha
28344937214SPrabhakar Kushwaha for (i = 0; i < 4; i++) {
28444937214SPrabhakar Kushwaha for (j = 0; j < 4; j++) {
28544937214SPrabhakar Kushwaha a = 0x18;
28644937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 6, 1, &a, 1);
28744937214SPrabhakar Kushwaha a = 0x38;
28844937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 4, 1, &a, 1);
28944937214SPrabhakar Kushwaha a = 0x4;
29044937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 8, 1, &a, 1);
29144937214SPrabhakar Kushwaha
29244937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
29344937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
29444937214SPrabhakar Kushwaha
29544937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
29644937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
29744937214SPrabhakar Kushwaha
29844937214SPrabhakar Kushwaha a = 0x14;
29944937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
30044937214SPrabhakar Kushwaha a = 0xb5;
30144937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
30244937214SPrabhakar Kushwaha a = 0x20;
30344937214SPrabhakar Kushwaha i2c_write(i2c_phy_addr, 4, 1, &a, 1);
30444937214SPrabhakar Kushwaha mdelay(100);
30544937214SPrabhakar Kushwaha ret = miiphy_read(dev, phy_addr, 0x11, &value);
30644937214SPrabhakar Kushwaha if (ret > 0)
30744937214SPrabhakar Kushwaha goto error;
30844937214SPrabhakar Kushwaha mdelay(1);
30944937214SPrabhakar Kushwaha ret = miiphy_read(dev, phy_addr, 0x11, &value);
31044937214SPrabhakar Kushwaha if (ret > 0)
31144937214SPrabhakar Kushwaha goto error;
31244937214SPrabhakar Kushwaha mdelay(10);
31344937214SPrabhakar Kushwaha if ((value & 0xf) == 0xf) {
31444937214SPrabhakar Kushwaha printf("DPMAC %d :PHY is ..... Configured\n",
31544937214SPrabhakar Kushwaha dpmac);
31644937214SPrabhakar Kushwaha return;
31744937214SPrabhakar Kushwaha }
31844937214SPrabhakar Kushwaha }
31944937214SPrabhakar Kushwaha }
32044937214SPrabhakar Kushwaha error:
32144937214SPrabhakar Kushwaha printf("DPMAC %d :PHY ..... FAILED to configure PHY\n", dpmac);
32244937214SPrabhakar Kushwaha return;
32344937214SPrabhakar Kushwaha }
32444937214SPrabhakar Kushwaha
ls2080a_qds_mdio_name_for_muxval(u8 muxval)32544937214SPrabhakar Kushwaha static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
32644937214SPrabhakar Kushwaha {
32744937214SPrabhakar Kushwaha return mdio_names[muxval];
32844937214SPrabhakar Kushwaha }
32944937214SPrabhakar Kushwaha
mii_dev_for_muxval(u8 muxval)33044937214SPrabhakar Kushwaha struct mii_dev *mii_dev_for_muxval(u8 muxval)
33144937214SPrabhakar Kushwaha {
33244937214SPrabhakar Kushwaha struct mii_dev *bus;
33344937214SPrabhakar Kushwaha const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
33444937214SPrabhakar Kushwaha
33544937214SPrabhakar Kushwaha if (!name) {
33644937214SPrabhakar Kushwaha printf("No bus for muxval %x\n", muxval);
33744937214SPrabhakar Kushwaha return NULL;
33844937214SPrabhakar Kushwaha }
33944937214SPrabhakar Kushwaha
34044937214SPrabhakar Kushwaha bus = miiphy_get_dev_by_name(name);
34144937214SPrabhakar Kushwaha
34244937214SPrabhakar Kushwaha if (!bus) {
34344937214SPrabhakar Kushwaha printf("No bus by name %s\n", name);
34444937214SPrabhakar Kushwaha return NULL;
34544937214SPrabhakar Kushwaha }
34644937214SPrabhakar Kushwaha
34744937214SPrabhakar Kushwaha return bus;
34844937214SPrabhakar Kushwaha }
34944937214SPrabhakar Kushwaha
ls2080a_qds_enable_SFP_TX(u8 muxval)35044937214SPrabhakar Kushwaha static void ls2080a_qds_enable_SFP_TX(u8 muxval)
35144937214SPrabhakar Kushwaha {
35244937214SPrabhakar Kushwaha u8 brdcfg9;
35344937214SPrabhakar Kushwaha
35444937214SPrabhakar Kushwaha brdcfg9 = QIXIS_READ(brdcfg[9]);
35544937214SPrabhakar Kushwaha brdcfg9 &= ~BRDCFG9_SFPTX_MASK;
35644937214SPrabhakar Kushwaha brdcfg9 |= (muxval << BRDCFG9_SFPTX_SHIFT);
35744937214SPrabhakar Kushwaha QIXIS_WRITE(brdcfg[9], brdcfg9);
35844937214SPrabhakar Kushwaha }
35944937214SPrabhakar Kushwaha
ls2080a_qds_mux_mdio(u8 muxval)36044937214SPrabhakar Kushwaha static void ls2080a_qds_mux_mdio(u8 muxval)
36144937214SPrabhakar Kushwaha {
36244937214SPrabhakar Kushwaha u8 brdcfg4;
36344937214SPrabhakar Kushwaha
36444937214SPrabhakar Kushwaha if (muxval <= 5) {
36544937214SPrabhakar Kushwaha brdcfg4 = QIXIS_READ(brdcfg[4]);
36644937214SPrabhakar Kushwaha brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
36744937214SPrabhakar Kushwaha brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
36844937214SPrabhakar Kushwaha QIXIS_WRITE(brdcfg[4], brdcfg4);
36944937214SPrabhakar Kushwaha }
37044937214SPrabhakar Kushwaha }
37144937214SPrabhakar Kushwaha
ls2080a_qds_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)37244937214SPrabhakar Kushwaha static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
37344937214SPrabhakar Kushwaha int devad, int regnum)
37444937214SPrabhakar Kushwaha {
37544937214SPrabhakar Kushwaha struct ls2080a_qds_mdio *priv = bus->priv;
37644937214SPrabhakar Kushwaha
37744937214SPrabhakar Kushwaha ls2080a_qds_mux_mdio(priv->muxval);
37844937214SPrabhakar Kushwaha
37944937214SPrabhakar Kushwaha return priv->realbus->read(priv->realbus, addr, devad, regnum);
38044937214SPrabhakar Kushwaha }
38144937214SPrabhakar Kushwaha
ls2080a_qds_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)38244937214SPrabhakar Kushwaha static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
38344937214SPrabhakar Kushwaha int regnum, u16 value)
38444937214SPrabhakar Kushwaha {
38544937214SPrabhakar Kushwaha struct ls2080a_qds_mdio *priv = bus->priv;
38644937214SPrabhakar Kushwaha
38744937214SPrabhakar Kushwaha ls2080a_qds_mux_mdio(priv->muxval);
38844937214SPrabhakar Kushwaha
38944937214SPrabhakar Kushwaha return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
39044937214SPrabhakar Kushwaha }
39144937214SPrabhakar Kushwaha
ls2080a_qds_mdio_reset(struct mii_dev * bus)39244937214SPrabhakar Kushwaha static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
39344937214SPrabhakar Kushwaha {
39444937214SPrabhakar Kushwaha struct ls2080a_qds_mdio *priv = bus->priv;
39544937214SPrabhakar Kushwaha
39644937214SPrabhakar Kushwaha return priv->realbus->reset(priv->realbus);
39744937214SPrabhakar Kushwaha }
39844937214SPrabhakar Kushwaha
ls2080a_qds_mdio_init(char * realbusname,u8 muxval)39944937214SPrabhakar Kushwaha static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
40044937214SPrabhakar Kushwaha {
40144937214SPrabhakar Kushwaha struct ls2080a_qds_mdio *pmdio;
40244937214SPrabhakar Kushwaha struct mii_dev *bus = mdio_alloc();
40344937214SPrabhakar Kushwaha
40444937214SPrabhakar Kushwaha if (!bus) {
40544937214SPrabhakar Kushwaha printf("Failed to allocate ls2080a_qds MDIO bus\n");
40644937214SPrabhakar Kushwaha return -1;
40744937214SPrabhakar Kushwaha }
40844937214SPrabhakar Kushwaha
40944937214SPrabhakar Kushwaha pmdio = malloc(sizeof(*pmdio));
41044937214SPrabhakar Kushwaha if (!pmdio) {
41144937214SPrabhakar Kushwaha printf("Failed to allocate ls2080a_qds private data\n");
41244937214SPrabhakar Kushwaha free(bus);
41344937214SPrabhakar Kushwaha return -1;
41444937214SPrabhakar Kushwaha }
41544937214SPrabhakar Kushwaha
41644937214SPrabhakar Kushwaha bus->read = ls2080a_qds_mdio_read;
41744937214SPrabhakar Kushwaha bus->write = ls2080a_qds_mdio_write;
41844937214SPrabhakar Kushwaha bus->reset = ls2080a_qds_mdio_reset;
419192bc694SBen Whitten strcpy(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
42044937214SPrabhakar Kushwaha
42144937214SPrabhakar Kushwaha pmdio->realbus = miiphy_get_dev_by_name(realbusname);
42244937214SPrabhakar Kushwaha
42344937214SPrabhakar Kushwaha if (!pmdio->realbus) {
42444937214SPrabhakar Kushwaha printf("No bus with name %s\n", realbusname);
42544937214SPrabhakar Kushwaha free(bus);
42644937214SPrabhakar Kushwaha free(pmdio);
42744937214SPrabhakar Kushwaha return -1;
42844937214SPrabhakar Kushwaha }
42944937214SPrabhakar Kushwaha
43044937214SPrabhakar Kushwaha pmdio->muxval = muxval;
43144937214SPrabhakar Kushwaha bus->priv = pmdio;
43244937214SPrabhakar Kushwaha
43344937214SPrabhakar Kushwaha return mdio_register(bus);
43444937214SPrabhakar Kushwaha }
43544937214SPrabhakar Kushwaha
43644937214SPrabhakar Kushwaha /*
43744937214SPrabhakar Kushwaha * Initialize the dpmac_info array.
43844937214SPrabhakar Kushwaha *
43944937214SPrabhakar Kushwaha */
initialize_dpmac_to_slot(void)44044937214SPrabhakar Kushwaha static void initialize_dpmac_to_slot(void)
44144937214SPrabhakar Kushwaha {
44244937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
44344937214SPrabhakar Kushwaha int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
44444937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
44544937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
44644937214SPrabhakar Kushwaha int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
44744937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
44844937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
44944937214SPrabhakar Kushwaha
45044937214SPrabhakar Kushwaha char *env_hwconfig;
45100caae6dSSimon Glass env_hwconfig = env_get("hwconfig");
45244937214SPrabhakar Kushwaha
45344937214SPrabhakar Kushwaha switch (serdes1_prtcl) {
45444937214SPrabhakar Kushwaha case 0x07:
45544937214SPrabhakar Kushwaha case 0x09:
45644937214SPrabhakar Kushwaha case 0x33:
45744937214SPrabhakar Kushwaha printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
45844937214SPrabhakar Kushwaha serdes1_prtcl);
45944937214SPrabhakar Kushwaha lane_to_slot_fsm1[0] = EMI1_SLOT1;
46044937214SPrabhakar Kushwaha lane_to_slot_fsm1[1] = EMI1_SLOT1;
46144937214SPrabhakar Kushwaha lane_to_slot_fsm1[2] = EMI1_SLOT1;
46244937214SPrabhakar Kushwaha lane_to_slot_fsm1[3] = EMI1_SLOT1;
46344937214SPrabhakar Kushwaha if (hwconfig_f("xqsgmii", env_hwconfig)) {
46444937214SPrabhakar Kushwaha lane_to_slot_fsm1[4] = EMI1_SLOT1;
46544937214SPrabhakar Kushwaha lane_to_slot_fsm1[5] = EMI1_SLOT1;
46644937214SPrabhakar Kushwaha lane_to_slot_fsm1[6] = EMI1_SLOT1;
46744937214SPrabhakar Kushwaha lane_to_slot_fsm1[7] = EMI1_SLOT1;
46844937214SPrabhakar Kushwaha } else {
46944937214SPrabhakar Kushwaha lane_to_slot_fsm1[4] = EMI1_SLOT2;
47044937214SPrabhakar Kushwaha lane_to_slot_fsm1[5] = EMI1_SLOT2;
47144937214SPrabhakar Kushwaha lane_to_slot_fsm1[6] = EMI1_SLOT2;
47244937214SPrabhakar Kushwaha lane_to_slot_fsm1[7] = EMI1_SLOT2;
47344937214SPrabhakar Kushwaha }
47444937214SPrabhakar Kushwaha break;
47544937214SPrabhakar Kushwaha
476fc35addeSPriyanka Jain case 0x39:
477fc35addeSPriyanka Jain printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
478fc35addeSPriyanka Jain serdes1_prtcl);
479fc35addeSPriyanka Jain if (hwconfig_f("xqsgmii", env_hwconfig)) {
480fc35addeSPriyanka Jain lane_to_slot_fsm1[0] = EMI1_SLOT3;
481fc35addeSPriyanka Jain lane_to_slot_fsm1[1] = EMI1_SLOT3;
482fc35addeSPriyanka Jain lane_to_slot_fsm1[2] = EMI1_SLOT3;
483fc35addeSPriyanka Jain lane_to_slot_fsm1[3] = EMI_NONE;
484fc35addeSPriyanka Jain } else {
485fc35addeSPriyanka Jain lane_to_slot_fsm1[0] = EMI_NONE;
486fc35addeSPriyanka Jain lane_to_slot_fsm1[1] = EMI_NONE;
487fc35addeSPriyanka Jain lane_to_slot_fsm1[2] = EMI_NONE;
488fc35addeSPriyanka Jain lane_to_slot_fsm1[3] = EMI_NONE;
489fc35addeSPriyanka Jain }
490fc35addeSPriyanka Jain lane_to_slot_fsm1[4] = EMI1_SLOT3;
491fc35addeSPriyanka Jain lane_to_slot_fsm1[5] = EMI1_SLOT3;
492fc35addeSPriyanka Jain lane_to_slot_fsm1[6] = EMI1_SLOT3;
493fc35addeSPriyanka Jain lane_to_slot_fsm1[7] = EMI_NONE;
494fc35addeSPriyanka Jain break;
495fc35addeSPriyanka Jain
496fc35addeSPriyanka Jain case 0x4D:
497fc35addeSPriyanka Jain printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
498fc35addeSPriyanka Jain serdes1_prtcl);
499fc35addeSPriyanka Jain if (hwconfig_f("xqsgmii", env_hwconfig)) {
500fc35addeSPriyanka Jain lane_to_slot_fsm1[0] = EMI1_SLOT3;
501fc35addeSPriyanka Jain lane_to_slot_fsm1[1] = EMI1_SLOT3;
502fc35addeSPriyanka Jain lane_to_slot_fsm1[2] = EMI_NONE;
503fc35addeSPriyanka Jain lane_to_slot_fsm1[3] = EMI_NONE;
504fc35addeSPriyanka Jain } else {
505fc35addeSPriyanka Jain lane_to_slot_fsm1[0] = EMI_NONE;
506fc35addeSPriyanka Jain lane_to_slot_fsm1[1] = EMI_NONE;
507fc35addeSPriyanka Jain lane_to_slot_fsm1[2] = EMI_NONE;
508fc35addeSPriyanka Jain lane_to_slot_fsm1[3] = EMI_NONE;
509fc35addeSPriyanka Jain }
510fc35addeSPriyanka Jain lane_to_slot_fsm1[4] = EMI1_SLOT3;
511fc35addeSPriyanka Jain lane_to_slot_fsm1[5] = EMI1_SLOT3;
512fc35addeSPriyanka Jain lane_to_slot_fsm1[6] = EMI_NONE;
513fc35addeSPriyanka Jain lane_to_slot_fsm1[7] = EMI_NONE;
514fc35addeSPriyanka Jain break;
515fc35addeSPriyanka Jain
51644937214SPrabhakar Kushwaha case 0x2A:
517fc35addeSPriyanka Jain case 0x4B:
518fc35addeSPriyanka Jain case 0x4C:
51944937214SPrabhakar Kushwaha printf("qds: WRIOP: Supported SerDes1 Protocol 0x%02x\n",
52044937214SPrabhakar Kushwaha serdes1_prtcl);
52144937214SPrabhakar Kushwaha break;
52244937214SPrabhakar Kushwaha default:
52344937214SPrabhakar Kushwaha printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
52444937214SPrabhakar Kushwaha __func__, serdes1_prtcl);
52544937214SPrabhakar Kushwaha break;
52644937214SPrabhakar Kushwaha }
52744937214SPrabhakar Kushwaha
52844937214SPrabhakar Kushwaha switch (serdes2_prtcl) {
52944937214SPrabhakar Kushwaha case 0x07:
53044937214SPrabhakar Kushwaha case 0x08:
53144937214SPrabhakar Kushwaha case 0x09:
53244937214SPrabhakar Kushwaha case 0x49:
53344937214SPrabhakar Kushwaha printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
53444937214SPrabhakar Kushwaha serdes2_prtcl);
53544937214SPrabhakar Kushwaha lane_to_slot_fsm2[0] = EMI1_SLOT4;
53644937214SPrabhakar Kushwaha lane_to_slot_fsm2[1] = EMI1_SLOT4;
53744937214SPrabhakar Kushwaha lane_to_slot_fsm2[2] = EMI1_SLOT4;
53844937214SPrabhakar Kushwaha lane_to_slot_fsm2[3] = EMI1_SLOT4;
53944937214SPrabhakar Kushwaha
54044937214SPrabhakar Kushwaha if (hwconfig_f("xqsgmii", env_hwconfig)) {
54144937214SPrabhakar Kushwaha lane_to_slot_fsm2[4] = EMI1_SLOT4;
54244937214SPrabhakar Kushwaha lane_to_slot_fsm2[5] = EMI1_SLOT4;
54344937214SPrabhakar Kushwaha lane_to_slot_fsm2[6] = EMI1_SLOT4;
54444937214SPrabhakar Kushwaha lane_to_slot_fsm2[7] = EMI1_SLOT4;
54544937214SPrabhakar Kushwaha } else {
54644937214SPrabhakar Kushwaha /* No MDIO physical connection */
54744937214SPrabhakar Kushwaha lane_to_slot_fsm2[4] = EMI1_SLOT6;
54844937214SPrabhakar Kushwaha lane_to_slot_fsm2[5] = EMI1_SLOT6;
54944937214SPrabhakar Kushwaha lane_to_slot_fsm2[6] = EMI1_SLOT6;
55044937214SPrabhakar Kushwaha lane_to_slot_fsm2[7] = EMI1_SLOT6;
55144937214SPrabhakar Kushwaha }
55244937214SPrabhakar Kushwaha break;
553fc35addeSPriyanka Jain
554fc35addeSPriyanka Jain case 0x47:
555fc35addeSPriyanka Jain printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
556fc35addeSPriyanka Jain serdes2_prtcl);
557fc35addeSPriyanka Jain lane_to_slot_fsm2[0] = EMI_NONE;
558fc35addeSPriyanka Jain lane_to_slot_fsm2[1] = EMI1_SLOT5;
559fc35addeSPriyanka Jain lane_to_slot_fsm2[2] = EMI1_SLOT5;
560fc35addeSPriyanka Jain lane_to_slot_fsm2[3] = EMI1_SLOT5;
561fc35addeSPriyanka Jain
562fc35addeSPriyanka Jain if (hwconfig_f("xqsgmii", env_hwconfig)) {
563fc35addeSPriyanka Jain lane_to_slot_fsm2[4] = EMI_NONE;
564fc35addeSPriyanka Jain lane_to_slot_fsm2[5] = EMI1_SLOT5;
565fc35addeSPriyanka Jain lane_to_slot_fsm2[6] = EMI1_SLOT5;
566fc35addeSPriyanka Jain lane_to_slot_fsm2[7] = EMI1_SLOT5;
567fc35addeSPriyanka Jain }
568fc35addeSPriyanka Jain break;
569fc35addeSPriyanka Jain
570fc35addeSPriyanka Jain case 0x57:
571fc35addeSPriyanka Jain printf("qds: WRIOP: Supported SerDes2 Protocol 0x%02x\n",
572fc35addeSPriyanka Jain serdes2_prtcl);
573fc35addeSPriyanka Jain if (hwconfig_f("xqsgmii", env_hwconfig)) {
574fc35addeSPriyanka Jain lane_to_slot_fsm2[0] = EMI_NONE;
575fc35addeSPriyanka Jain lane_to_slot_fsm2[1] = EMI_NONE;
576fc35addeSPriyanka Jain lane_to_slot_fsm2[2] = EMI_NONE;
577fc35addeSPriyanka Jain lane_to_slot_fsm2[3] = EMI_NONE;
578fc35addeSPriyanka Jain }
579fc35addeSPriyanka Jain lane_to_slot_fsm2[4] = EMI_NONE;
580fc35addeSPriyanka Jain lane_to_slot_fsm2[5] = EMI_NONE;
581fc35addeSPriyanka Jain lane_to_slot_fsm2[6] = EMI1_SLOT5;
582fc35addeSPriyanka Jain lane_to_slot_fsm2[7] = EMI1_SLOT5;
583fc35addeSPriyanka Jain break;
584fc35addeSPriyanka Jain
58544937214SPrabhakar Kushwaha default:
58644937214SPrabhakar Kushwaha printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
58744937214SPrabhakar Kushwaha __func__ , serdes2_prtcl);
58844937214SPrabhakar Kushwaha break;
58944937214SPrabhakar Kushwaha }
59044937214SPrabhakar Kushwaha }
59144937214SPrabhakar Kushwaha
ls2080a_handle_phy_interface_sgmii(int dpmac_id)59244937214SPrabhakar Kushwaha void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
59344937214SPrabhakar Kushwaha {
59444937214SPrabhakar Kushwaha int lane, slot;
59544937214SPrabhakar Kushwaha struct mii_dev *bus;
59644937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
59744937214SPrabhakar Kushwaha int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
59844937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
59944937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
60044937214SPrabhakar Kushwaha int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
60144937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
60244937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
60344937214SPrabhakar Kushwaha
60444937214SPrabhakar Kushwaha int *riser_phy_addr;
60500caae6dSSimon Glass char *env_hwconfig = env_get("hwconfig");
60644937214SPrabhakar Kushwaha
60744937214SPrabhakar Kushwaha if (hwconfig_f("xqsgmii", env_hwconfig))
60844937214SPrabhakar Kushwaha riser_phy_addr = &xqsgii_riser_phy_addr[0];
60944937214SPrabhakar Kushwaha else
61044937214SPrabhakar Kushwaha riser_phy_addr = &sgmii_riser_phy_addr[0];
61144937214SPrabhakar Kushwaha
61244937214SPrabhakar Kushwaha if (dpmac_id > WRIOP1_DPMAC9)
61344937214SPrabhakar Kushwaha goto serdes2;
61444937214SPrabhakar Kushwaha
61544937214SPrabhakar Kushwaha switch (serdes1_prtcl) {
61644937214SPrabhakar Kushwaha case 0x07:
617fc35addeSPriyanka Jain case 0x39:
618fc35addeSPriyanka Jain case 0x4D:
619fc35addeSPriyanka Jain lane = serdes_get_first_lane(FSL_SRDS_1, SGMII1 + dpmac_id - 1);
62044937214SPrabhakar Kushwaha
62144937214SPrabhakar Kushwaha slot = lane_to_slot_fsm1[lane];
62244937214SPrabhakar Kushwaha
62344937214SPrabhakar Kushwaha switch (++slot) {
62444937214SPrabhakar Kushwaha case 1:
62544937214SPrabhakar Kushwaha /* Slot housing a SGMII riser card? */
626*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
62744937214SPrabhakar Kushwaha riser_phy_addr[dpmac_id - 1]);
62844937214SPrabhakar Kushwaha dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
62944937214SPrabhakar Kushwaha bus = mii_dev_for_muxval(EMI1_SLOT1);
63044937214SPrabhakar Kushwaha wriop_set_mdio(dpmac_id, bus);
63144937214SPrabhakar Kushwaha break;
63244937214SPrabhakar Kushwaha case 2:
63344937214SPrabhakar Kushwaha /* Slot housing a SGMII riser card? */
634*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
63544937214SPrabhakar Kushwaha riser_phy_addr[dpmac_id - 1]);
63644937214SPrabhakar Kushwaha dpmac_info[dpmac_id].board_mux = EMI1_SLOT2;
63744937214SPrabhakar Kushwaha bus = mii_dev_for_muxval(EMI1_SLOT2);
63844937214SPrabhakar Kushwaha wriop_set_mdio(dpmac_id, bus);
63944937214SPrabhakar Kushwaha break;
64044937214SPrabhakar Kushwaha case 3:
641fc35addeSPriyanka Jain if (slot == EMI_NONE)
642fc35addeSPriyanka Jain return;
643fc35addeSPriyanka Jain if (serdes1_prtcl == 0x39) {
644*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
645fc35addeSPriyanka Jain riser_phy_addr[dpmac_id - 2]);
646fc35addeSPriyanka Jain if (dpmac_id >= 6 && hwconfig_f("xqsgmii",
647fc35addeSPriyanka Jain env_hwconfig))
648*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
649fc35addeSPriyanka Jain riser_phy_addr[dpmac_id - 3]);
650fc35addeSPriyanka Jain } else {
651*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
652fc35addeSPriyanka Jain riser_phy_addr[dpmac_id - 2]);
653fc35addeSPriyanka Jain if (dpmac_id >= 7 && hwconfig_f("xqsgmii",
654fc35addeSPriyanka Jain env_hwconfig))
655*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
656fc35addeSPriyanka Jain riser_phy_addr[dpmac_id - 3]);
657fc35addeSPriyanka Jain }
658fc35addeSPriyanka Jain dpmac_info[dpmac_id].board_mux = EMI1_SLOT3;
659fc35addeSPriyanka Jain bus = mii_dev_for_muxval(EMI1_SLOT3);
660fc35addeSPriyanka Jain wriop_set_mdio(dpmac_id, bus);
66144937214SPrabhakar Kushwaha break;
66244937214SPrabhakar Kushwaha case 4:
66344937214SPrabhakar Kushwaha break;
66444937214SPrabhakar Kushwaha case 5:
66544937214SPrabhakar Kushwaha break;
66644937214SPrabhakar Kushwaha case 6:
66744937214SPrabhakar Kushwaha break;
66844937214SPrabhakar Kushwaha }
66944937214SPrabhakar Kushwaha break;
67044937214SPrabhakar Kushwaha default:
67144937214SPrabhakar Kushwaha printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
67244937214SPrabhakar Kushwaha __func__ , serdes1_prtcl);
67344937214SPrabhakar Kushwaha break;
67444937214SPrabhakar Kushwaha }
67544937214SPrabhakar Kushwaha
67644937214SPrabhakar Kushwaha serdes2:
67744937214SPrabhakar Kushwaha switch (serdes2_prtcl) {
67844937214SPrabhakar Kushwaha case 0x07:
67944937214SPrabhakar Kushwaha case 0x08:
68044937214SPrabhakar Kushwaha case 0x49:
681fc35addeSPriyanka Jain case 0x47:
682fc35addeSPriyanka Jain case 0x57:
68344937214SPrabhakar Kushwaha lane = serdes_get_first_lane(FSL_SRDS_2, SGMII9 +
68444937214SPrabhakar Kushwaha (dpmac_id - 9));
68544937214SPrabhakar Kushwaha slot = lane_to_slot_fsm2[lane];
68644937214SPrabhakar Kushwaha
68744937214SPrabhakar Kushwaha switch (++slot) {
68844937214SPrabhakar Kushwaha case 1:
68944937214SPrabhakar Kushwaha break;
69044937214SPrabhakar Kushwaha case 3:
69144937214SPrabhakar Kushwaha break;
69244937214SPrabhakar Kushwaha case 4:
69344937214SPrabhakar Kushwaha /* Slot housing a SGMII riser card? */
694*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
69544937214SPrabhakar Kushwaha riser_phy_addr[dpmac_id - 9]);
69644937214SPrabhakar Kushwaha dpmac_info[dpmac_id].board_mux = EMI1_SLOT4;
69744937214SPrabhakar Kushwaha bus = mii_dev_for_muxval(EMI1_SLOT4);
69844937214SPrabhakar Kushwaha wriop_set_mdio(dpmac_id, bus);
69944937214SPrabhakar Kushwaha break;
70044937214SPrabhakar Kushwaha case 5:
701fc35addeSPriyanka Jain if (slot == EMI_NONE)
702fc35addeSPriyanka Jain return;
703fc35addeSPriyanka Jain if (serdes2_prtcl == 0x47) {
704*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
705fc35addeSPriyanka Jain riser_phy_addr[dpmac_id - 10]);
706fc35addeSPriyanka Jain if (dpmac_id >= 14 && hwconfig_f("xqsgmii",
707fc35addeSPriyanka Jain env_hwconfig))
708*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
709fc35addeSPriyanka Jain riser_phy_addr[dpmac_id - 11]);
710fc35addeSPriyanka Jain } else {
711*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
712fc35addeSPriyanka Jain riser_phy_addr[dpmac_id - 11]);
713fc35addeSPriyanka Jain }
714fc35addeSPriyanka Jain dpmac_info[dpmac_id].board_mux = EMI1_SLOT5;
715fc35addeSPriyanka Jain bus = mii_dev_for_muxval(EMI1_SLOT5);
716fc35addeSPriyanka Jain wriop_set_mdio(dpmac_id, bus);
71744937214SPrabhakar Kushwaha break;
71844937214SPrabhakar Kushwaha case 6:
71944937214SPrabhakar Kushwaha /* Slot housing a SGMII riser card? */
720*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0,
72144937214SPrabhakar Kushwaha riser_phy_addr[dpmac_id - 13]);
72244937214SPrabhakar Kushwaha dpmac_info[dpmac_id].board_mux = EMI1_SLOT6;
72344937214SPrabhakar Kushwaha bus = mii_dev_for_muxval(EMI1_SLOT6);
72444937214SPrabhakar Kushwaha wriop_set_mdio(dpmac_id, bus);
72544937214SPrabhakar Kushwaha break;
72644937214SPrabhakar Kushwaha }
72744937214SPrabhakar Kushwaha break;
72844937214SPrabhakar Kushwaha default:
72944937214SPrabhakar Kushwaha printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
73044937214SPrabhakar Kushwaha __func__, serdes2_prtcl);
73144937214SPrabhakar Kushwaha break;
73244937214SPrabhakar Kushwaha }
73344937214SPrabhakar Kushwaha }
73444937214SPrabhakar Kushwaha
ls2080a_handle_phy_interface_qsgmii(int dpmac_id)73544937214SPrabhakar Kushwaha void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
73644937214SPrabhakar Kushwaha {
73744937214SPrabhakar Kushwaha int lane = 0, slot;
73844937214SPrabhakar Kushwaha struct mii_dev *bus;
73944937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
74044937214SPrabhakar Kushwaha int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
74144937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
74244937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
74344937214SPrabhakar Kushwaha
74444937214SPrabhakar Kushwaha switch (serdes1_prtcl) {
74544937214SPrabhakar Kushwaha case 0x33:
74644937214SPrabhakar Kushwaha switch (dpmac_id) {
74744937214SPrabhakar Kushwaha case 1:
74844937214SPrabhakar Kushwaha case 2:
74944937214SPrabhakar Kushwaha case 3:
75044937214SPrabhakar Kushwaha case 4:
75144937214SPrabhakar Kushwaha lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_A);
75244937214SPrabhakar Kushwaha break;
75344937214SPrabhakar Kushwaha case 5:
75444937214SPrabhakar Kushwaha case 6:
75544937214SPrabhakar Kushwaha case 7:
75644937214SPrabhakar Kushwaha case 8:
75744937214SPrabhakar Kushwaha lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_B);
75844937214SPrabhakar Kushwaha break;
75944937214SPrabhakar Kushwaha case 9:
76044937214SPrabhakar Kushwaha case 10:
76144937214SPrabhakar Kushwaha case 11:
76244937214SPrabhakar Kushwaha case 12:
76344937214SPrabhakar Kushwaha lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_C);
76444937214SPrabhakar Kushwaha break;
76544937214SPrabhakar Kushwaha case 13:
76644937214SPrabhakar Kushwaha case 14:
76744937214SPrabhakar Kushwaha case 15:
76844937214SPrabhakar Kushwaha case 16:
76944937214SPrabhakar Kushwaha lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_D);
77044937214SPrabhakar Kushwaha break;
77144937214SPrabhakar Kushwaha }
77244937214SPrabhakar Kushwaha
77344937214SPrabhakar Kushwaha slot = lane_to_slot_fsm1[lane];
77444937214SPrabhakar Kushwaha
77544937214SPrabhakar Kushwaha switch (++slot) {
77644937214SPrabhakar Kushwaha case 1:
77744937214SPrabhakar Kushwaha /* Slot housing a QSGMII riser card? */
778*1a048cd6SPankaj Bansal wriop_set_phy_address(dpmac_id, 0, dpmac_id - 1);
77944937214SPrabhakar Kushwaha dpmac_info[dpmac_id].board_mux = EMI1_SLOT1;
78044937214SPrabhakar Kushwaha bus = mii_dev_for_muxval(EMI1_SLOT1);
78144937214SPrabhakar Kushwaha wriop_set_mdio(dpmac_id, bus);
78244937214SPrabhakar Kushwaha break;
78344937214SPrabhakar Kushwaha case 3:
78444937214SPrabhakar Kushwaha break;
78544937214SPrabhakar Kushwaha case 4:
78644937214SPrabhakar Kushwaha break;
78744937214SPrabhakar Kushwaha case 5:
78844937214SPrabhakar Kushwaha break;
78944937214SPrabhakar Kushwaha case 6:
79044937214SPrabhakar Kushwaha break;
79144937214SPrabhakar Kushwaha }
79244937214SPrabhakar Kushwaha break;
79344937214SPrabhakar Kushwaha default:
79444937214SPrabhakar Kushwaha printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
79544937214SPrabhakar Kushwaha serdes1_prtcl);
79644937214SPrabhakar Kushwaha break;
79744937214SPrabhakar Kushwaha }
79844937214SPrabhakar Kushwaha
79944937214SPrabhakar Kushwaha qsgmii_configure_repeater(dpmac_id);
80044937214SPrabhakar Kushwaha }
80144937214SPrabhakar Kushwaha
ls2080a_handle_phy_interface_xsgmii(int i)80244937214SPrabhakar Kushwaha void ls2080a_handle_phy_interface_xsgmii(int i)
80344937214SPrabhakar Kushwaha {
80444937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
80544937214SPrabhakar Kushwaha int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
80644937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
80744937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
80844937214SPrabhakar Kushwaha
80944937214SPrabhakar Kushwaha switch (serdes1_prtcl) {
81044937214SPrabhakar Kushwaha case 0x2A:
811fc35addeSPriyanka Jain case 0x4B:
812fc35addeSPriyanka Jain case 0x4C:
81344937214SPrabhakar Kushwaha /*
814a187559eSBin Meng * XFI does not need a PHY to work, but to avoid U-Boot use
81544937214SPrabhakar Kushwaha * default PHY address which is zero to a MAC when it found
81644937214SPrabhakar Kushwaha * a MAC has no PHY address, we give a PHY address to XFI
81744937214SPrabhakar Kushwaha * MAC, and should not use a real XAUI PHY address, since
81844937214SPrabhakar Kushwaha * MDIO can access it successfully, and then MDIO thinks
81944937214SPrabhakar Kushwaha * the XAUI card is used for the XFI MAC, which will cause
82044937214SPrabhakar Kushwaha * error.
82144937214SPrabhakar Kushwaha */
822*1a048cd6SPankaj Bansal wriop_set_phy_address(i, 0, i + 4);
82344937214SPrabhakar Kushwaha ls2080a_qds_enable_SFP_TX(SFP_TX);
82444937214SPrabhakar Kushwaha
82544937214SPrabhakar Kushwaha break;
82644937214SPrabhakar Kushwaha default:
82744937214SPrabhakar Kushwaha printf("qds: WRIOP: Unsupported SerDes Protocol 0x%02x\n",
82844937214SPrabhakar Kushwaha serdes1_prtcl);
82944937214SPrabhakar Kushwaha break;
83044937214SPrabhakar Kushwaha }
83144937214SPrabhakar Kushwaha }
83244937214SPrabhakar Kushwaha #endif
83344937214SPrabhakar Kushwaha
board_eth_init(bd_t * bis)83444937214SPrabhakar Kushwaha int board_eth_init(bd_t *bis)
83544937214SPrabhakar Kushwaha {
83644937214SPrabhakar Kushwaha int error;
8371f55a938SSantan Kumar #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
83844937214SPrabhakar Kushwaha struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
83944937214SPrabhakar Kushwaha int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
84044937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
84144937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
84244937214SPrabhakar Kushwaha int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
84344937214SPrabhakar Kushwaha FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
84444937214SPrabhakar Kushwaha >> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
84544937214SPrabhakar Kushwaha
84644937214SPrabhakar Kushwaha struct memac_mdio_info *memac_mdio0_info;
84744937214SPrabhakar Kushwaha struct memac_mdio_info *memac_mdio1_info;
84844937214SPrabhakar Kushwaha unsigned int i;
84944937214SPrabhakar Kushwaha char *env_hwconfig;
85044937214SPrabhakar Kushwaha
85100caae6dSSimon Glass env_hwconfig = env_get("hwconfig");
85244937214SPrabhakar Kushwaha
85344937214SPrabhakar Kushwaha initialize_dpmac_to_slot();
85444937214SPrabhakar Kushwaha
85544937214SPrabhakar Kushwaha memac_mdio0_info = (struct memac_mdio_info *)malloc(
85644937214SPrabhakar Kushwaha sizeof(struct memac_mdio_info));
85744937214SPrabhakar Kushwaha memac_mdio0_info->regs =
85844937214SPrabhakar Kushwaha (struct memac_mdio_controller *)
85944937214SPrabhakar Kushwaha CONFIG_SYS_FSL_WRIOP1_MDIO1;
86044937214SPrabhakar Kushwaha memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
86144937214SPrabhakar Kushwaha
86244937214SPrabhakar Kushwaha /* Register the real MDIO1 bus */
86344937214SPrabhakar Kushwaha fm_memac_mdio_init(bis, memac_mdio0_info);
86444937214SPrabhakar Kushwaha
86544937214SPrabhakar Kushwaha memac_mdio1_info = (struct memac_mdio_info *)malloc(
86644937214SPrabhakar Kushwaha sizeof(struct memac_mdio_info));
86744937214SPrabhakar Kushwaha memac_mdio1_info->regs =
86844937214SPrabhakar Kushwaha (struct memac_mdio_controller *)
86944937214SPrabhakar Kushwaha CONFIG_SYS_FSL_WRIOP1_MDIO2;
87044937214SPrabhakar Kushwaha memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
87144937214SPrabhakar Kushwaha
87244937214SPrabhakar Kushwaha /* Register the real MDIO2 bus */
87344937214SPrabhakar Kushwaha fm_memac_mdio_init(bis, memac_mdio1_info);
87444937214SPrabhakar Kushwaha
87544937214SPrabhakar Kushwaha /* Register the muxing front-ends to the MDIO buses */
87644937214SPrabhakar Kushwaha ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
87744937214SPrabhakar Kushwaha ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
87844937214SPrabhakar Kushwaha ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
87944937214SPrabhakar Kushwaha ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
88044937214SPrabhakar Kushwaha ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
88144937214SPrabhakar Kushwaha ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
88244937214SPrabhakar Kushwaha
88344937214SPrabhakar Kushwaha ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
88444937214SPrabhakar Kushwaha
88544937214SPrabhakar Kushwaha for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
88644937214SPrabhakar Kushwaha switch (wriop_get_enet_if(i)) {
88744937214SPrabhakar Kushwaha case PHY_INTERFACE_MODE_QSGMII:
88844937214SPrabhakar Kushwaha ls2080a_handle_phy_interface_qsgmii(i);
88944937214SPrabhakar Kushwaha break;
89044937214SPrabhakar Kushwaha case PHY_INTERFACE_MODE_SGMII:
89144937214SPrabhakar Kushwaha ls2080a_handle_phy_interface_sgmii(i);
89244937214SPrabhakar Kushwaha break;
89344937214SPrabhakar Kushwaha case PHY_INTERFACE_MODE_XGMII:
89444937214SPrabhakar Kushwaha ls2080a_handle_phy_interface_xsgmii(i);
89544937214SPrabhakar Kushwaha break;
89644937214SPrabhakar Kushwaha default:
89744937214SPrabhakar Kushwaha break;
89844937214SPrabhakar Kushwaha
89944937214SPrabhakar Kushwaha if (i == 16)
90044937214SPrabhakar Kushwaha i = NUM_WRIOP_PORTS;
90144937214SPrabhakar Kushwaha }
90244937214SPrabhakar Kushwaha }
90344937214SPrabhakar Kushwaha
90444937214SPrabhakar Kushwaha error = cpu_eth_init(bis);
90544937214SPrabhakar Kushwaha
90644937214SPrabhakar Kushwaha if (hwconfig_f("xqsgmii", env_hwconfig)) {
90744937214SPrabhakar Kushwaha if (serdes1_prtcl == 0x7)
90844937214SPrabhakar Kushwaha sgmii_configure_repeater(1);
90944937214SPrabhakar Kushwaha if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
91044937214SPrabhakar Kushwaha serdes2_prtcl == 0x49)
91144937214SPrabhakar Kushwaha sgmii_configure_repeater(2);
91244937214SPrabhakar Kushwaha }
91344937214SPrabhakar Kushwaha #endif
91444937214SPrabhakar Kushwaha error = pci_eth_init(bis);
91544937214SPrabhakar Kushwaha return error;
91644937214SPrabhakar Kushwaha }
91744937214SPrabhakar Kushwaha
91833a8991aSBogdan Purcareata #if defined(CONFIG_RESET_PHY_R)
reset_phy(void)91933a8991aSBogdan Purcareata void reset_phy(void)
92033a8991aSBogdan Purcareata {
92133a8991aSBogdan Purcareata mc_env_boot();
92233a8991aSBogdan Purcareata }
92333a8991aSBogdan Purcareata #endif /* CONFIG_RESET_PHY_R */
924