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Searched refs:per_pll (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_s10.c32 writel(val, &clock_manager_base->per_pll.bypass); in cm_write_bypass_perpll()
93 &clock_manager_base->per_pll.pllglob); in cm_basic_init()
104 setbits_le32(&clock_manager_base->per_pll.pllglob, in cm_basic_init()
128 writel(0xff, &clock_manager_base->per_pll.cntr2clk); in cm_basic_init()
129 writel(0xff, &clock_manager_base->per_pll.cntr3clk); in cm_basic_init()
130 writel(0xff, &clock_manager_base->per_pll.cntr4clk); in cm_basic_init()
131 writel(0xff, &clock_manager_base->per_pll.cntr5clk); in cm_basic_init()
132 writel(0xff, &clock_manager_base->per_pll.cntr6clk); in cm_basic_init()
166 writel(~0, &clock_manager_base->per_pll.en); in cm_basic_init()
208 reg = readl(&clock_manager_base->per_pll.pllglob); in cm_get_per_vco_clk_hz()
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H A Dclock_manager_gen5.c82 readl(&clock_manager_base->per_pll.en), in cm_basic_init()
83 &clock_manager_base->per_pll.en); in cm_basic_init()
97 writel(0, &clock_manager_base->per_pll.en); in cm_basic_init()
109 &clock_manager_base->per_pll.vco); in cm_basic_init()
122 &clock_manager_base->per_pll.src); in cm_basic_init()
128 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
197 &clock_manager_base->per_pll.vco); in cm_basic_init()
244 &clock_manager_base->per_pll.vco); in cm_basic_init()
257 &clock_manager_base->per_pll.vco); in cm_basic_init()
307 writel(~0, &clock_manager_base->per_pll.en); in cm_basic_init()
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H A Dclock_manager_arria10.c584 &clock_manager_base->per_pll.vco1); in cm_pll_ramp_periph()
644 writel(0, &clock_manager_base->per_pll.en); in cm_full_cfg()
650 &clock_manager_base->per_pll.bypasss); in cm_full_cfg()
665 &clock_manager_base->per_pll.vco0); in cm_full_cfg()
713 &clock_manager_base->per_pll.vco1); in cm_full_cfg()
717 &clock_manager_base->per_pll.vco1); in cm_full_cfg()
741 &clock_manager_base->per_pll.vco0); in cm_full_cfg()
777 &clock_manager_base->per_pll.cntr2clk); in cm_full_cfg()
827 &clock_manager_base->per_pll.gpiodiv); in cm_full_cfg()
836 &clock_manager_base->per_pll.emacctl); in cm_full_cfg()
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/openbmc/u-boot/drivers/mmc/
H A Dsocfpga_dw_mmc.c59 clrbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
70 setbits_le32(&clock_manager_base->per_pll.en, in socfpga_dwmci_clksel()
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_s10.h139 struct socfpga_clock_manager_per_pll per_pll; member
H A Dclock_manager_arria10.h88 struct socfpga_clock_manager_per_pll per_pll; member
H A Dclock_manager_gen5.h108 struct socfpga_clock_manager_per_pll per_pll; member