32 	writel(val, &clock_manager_base->per_pll.bypass);  in cm_write_bypass_perpll()
93 		&clock_manager_base->per_pll.pllglob);  in cm_basic_init()
94 	writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);  in cm_basic_init()
95 	writel(vcocalib, &clock_manager_base->per_pll.vcocalib);  in cm_basic_init()
96 	writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);  in cm_basic_init()
97 	writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);  in cm_basic_init()
98 	writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);  in cm_basic_init()
99 	writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);  in cm_basic_init()
104 	setbits_le32(&clock_manager_base->per_pll.pllglob,  in cm_basic_init()
128 	writel(0xff, &clock_manager_base->per_pll.cntr2clk);  in cm_basic_init()
129 	writel(0xff, &clock_manager_base->per_pll.cntr3clk);  in cm_basic_init()
130 	writel(0xff, &clock_manager_base->per_pll.cntr4clk);  in cm_basic_init()
131 	writel(0xff, &clock_manager_base->per_pll.cntr5clk);  in cm_basic_init()
132 	writel(0xff, &clock_manager_base->per_pll.cntr6clk);  in cm_basic_init()
133 	writel(0xff, &clock_manager_base->per_pll.cntr7clk);  in cm_basic_init()
134 	writel(0xff, &clock_manager_base->per_pll.cntr8clk);  in cm_basic_init()
135 	writel(0xff, &clock_manager_base->per_pll.cntr9clk);  in cm_basic_init()
147 	writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);  in cm_basic_init()
148 	writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);  in cm_basic_init()
149 	writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);  in cm_basic_init()
150 	writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);  in cm_basic_init()
151 	writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);  in cm_basic_init()
152 	writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);  in cm_basic_init()
153 	writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);  in cm_basic_init()
154 	writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);  in cm_basic_init()
166 	writel(~0, &clock_manager_base->per_pll.en);  in cm_basic_init()
208 	reg = readl(&clock_manager_base->per_pll.pllglob);  in cm_get_per_vco_clk_hz()
227 	reg = readl(&clock_manager_base->per_pll.fdbck);  in cm_get_per_vco_clk_hz()
250 		clock /= (readl(&clock_manager_base->per_pll.pllc0) &  in cm_get_mpu_clk_hz()
287 		clock /= (readl(&clock_manager_base->per_pll.pllc1) &  in cm_get_l3_main_clk_hz()
311 	u32 clock = readl(&clock_manager_base->per_pll.cntr6clk);  in cm_get_mmc_controller_clk_hz()
324 		clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &  in cm_get_mmc_controller_clk_hz()