584 			&clock_manager_base->per_pll.vco1);  in cm_pll_ramp_periph()
589 		per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);  in cm_pll_ramp_periph()
644 	writel(0, &clock_manager_base->per_pll.en);  in cm_full_cfg()
650 	       &clock_manager_base->per_pll.bypasss);  in cm_full_cfg()
665 	       &clock_manager_base->per_pll.vco0);  in cm_full_cfg()
668 	writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);  in cm_full_cfg()
713 			&clock_manager_base->per_pll.vco1);  in cm_full_cfg()
717 			&clock_manager_base->per_pll.vco1);  in cm_full_cfg()
726 	clrbits_le32(&clock_manager_base->per_pll.vco0,  in cm_full_cfg()
738 	writel((readl(&clock_manager_base->per_pll.vco0) &  in cm_full_cfg()
741 		&clock_manager_base->per_pll.vco0);  in cm_full_cfg()
777 	       &clock_manager_base->per_pll.cntr2clk);  in cm_full_cfg()
781 	       &clock_manager_base->per_pll.cntr3clk);  in cm_full_cfg()
785 	       &clock_manager_base->per_pll.cntr4clk);  in cm_full_cfg()
789 	       &clock_manager_base->per_pll.cntr5clk);  in cm_full_cfg()
793 	       &clock_manager_base->per_pll.cntr6clk);  in cm_full_cfg()
795 	writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);  in cm_full_cfg()
799 	       &clock_manager_base->per_pll.cntr8clk);  in cm_full_cfg()
801 	writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);  in cm_full_cfg()
827 	       &clock_manager_base->per_pll.gpiodiv);  in cm_full_cfg()
836 	       &clock_manager_base->per_pll.emacctl);  in cm_full_cfg()
849 	setbits_le32(&clock_manager_base->per_pll.vco0,  in cm_full_cfg()
855 	clrbits_le32(&clock_manager_base->per_pll.vco0,  in cm_full_cfg()
867 	       &clock_manager_base->per_pll.bypassr);  in cm_full_cfg()
887 	writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);  in cm_full_cfg()