183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2c5c1af21SChin Liang See /*
3c5c1af21SChin Liang See * (C) Copyright 2013 Altera Corporation <www.altera.com>
4c5c1af21SChin Liang See */
5c5c1af21SChin Liang See
6c5c1af21SChin Liang See #include <common.h>
7c35ed77aSMarek Vasut #include <asm/arch/clock_manager.h>
8c35ed77aSMarek Vasut #include <asm/arch/system_manager.h>
9*12ea13adSMarek Vasut #include <clk.h>
10c35ed77aSMarek Vasut #include <dm.h>
11c5c1af21SChin Liang See #include <dwmmc.h>
12498d1a62SPavel Machek #include <errno.h>
13c35ed77aSMarek Vasut #include <fdtdec.h>
14b08c8c48SMasahiro Yamada #include <linux/libfdt.h>
15c35ed77aSMarek Vasut #include <linux/err.h>
16c35ed77aSMarek Vasut #include <malloc.h>
172d4d6937SLey Foon Tan #include <reset.h>
18c35ed77aSMarek Vasut
19c35ed77aSMarek Vasut DECLARE_GLOBAL_DATA_PTR;
20c5c1af21SChin Liang See
21c5c1af21SChin Liang See static const struct socfpga_clock_manager *clock_manager_base =
22c5c1af21SChin Liang See (void *)SOCFPGA_CLKMGR_ADDRESS;
23c5c1af21SChin Liang See static const struct socfpga_system_manager *system_manager_base =
24c5c1af21SChin Liang See (void *)SOCFPGA_SYSMGR_ADDRESS;
25c5c1af21SChin Liang See
26f1a485aaSSimon Glass struct socfpga_dwmci_plat {
27f1a485aaSSimon Glass struct mmc_config cfg;
28f1a485aaSSimon Glass struct mmc mmc;
29f1a485aaSSimon Glass };
30f1a485aaSSimon Glass
31c35ed77aSMarek Vasut /* socfpga implmentation specific driver private data */
329a41404dSChin Liang See struct dwmci_socfpga_priv_data {
33c35ed77aSMarek Vasut struct dwmci_host host;
34c5c1af21SChin Liang See unsigned int drvsel;
35c5c1af21SChin Liang See unsigned int smplsel;
369a41404dSChin Liang See };
379a41404dSChin Liang See
socfpga_dwmci_reset(struct udevice * dev)382d4d6937SLey Foon Tan static void socfpga_dwmci_reset(struct udevice *dev)
392d4d6937SLey Foon Tan {
402d4d6937SLey Foon Tan struct reset_ctl_bulk reset_bulk;
412d4d6937SLey Foon Tan int ret;
422d4d6937SLey Foon Tan
432d4d6937SLey Foon Tan ret = reset_get_bulk(dev, &reset_bulk);
442d4d6937SLey Foon Tan if (ret) {
452d4d6937SLey Foon Tan dev_warn(dev, "Can't get reset: %d\n", ret);
462d4d6937SLey Foon Tan return;
472d4d6937SLey Foon Tan }
482d4d6937SLey Foon Tan
492d4d6937SLey Foon Tan reset_deassert_bulk(&reset_bulk);
502d4d6937SLey Foon Tan }
512d4d6937SLey Foon Tan
socfpga_dwmci_clksel(struct dwmci_host * host)529a41404dSChin Liang See static void socfpga_dwmci_clksel(struct dwmci_host *host)
539a41404dSChin Liang See {
549a41404dSChin Liang See struct dwmci_socfpga_priv_data *priv = host->priv;
55a1684b61SDinh Nguyen u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) |
56a1684b61SDinh Nguyen ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT);
57c5c1af21SChin Liang See
58c5c1af21SChin Liang See /* Disable SDMMC clock. */
5951fb455fSPavel Machek clrbits_le32(&clock_manager_base->per_pll.en,
60c5c1af21SChin Liang See CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
61c5c1af21SChin Liang See
629a41404dSChin Liang See debug("%s: drvsel %d smplsel %d\n", __func__,
639a41404dSChin Liang See priv->drvsel, priv->smplsel);
64a1684b61SDinh Nguyen writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
65c5c1af21SChin Liang See
66c5c1af21SChin Liang See debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
67c5c1af21SChin Liang See readl(&system_manager_base->sdmmcgrp_ctrl));
68c5c1af21SChin Liang See
69c5c1af21SChin Liang See /* Enable SDMMC clock */
7051fb455fSPavel Machek setbits_le32(&clock_manager_base->per_pll.en,
71c5c1af21SChin Liang See CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
72c5c1af21SChin Liang See }
73c5c1af21SChin Liang See
socfpga_dwmmc_get_clk_rate(struct udevice * dev)74*12ea13adSMarek Vasut static int socfpga_dwmmc_get_clk_rate(struct udevice *dev)
75c5c1af21SChin Liang See {
76c35ed77aSMarek Vasut struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
77c35ed77aSMarek Vasut struct dwmci_host *host = &priv->host;
78*12ea13adSMarek Vasut #if CONFIG_IS_ENABLED(CLK)
79*12ea13adSMarek Vasut struct clk clk;
80*12ea13adSMarek Vasut int ret;
81498d1a62SPavel Machek
82*12ea13adSMarek Vasut ret = clk_get_by_index(dev, 1, &clk);
83*12ea13adSMarek Vasut if (ret)
84*12ea13adSMarek Vasut return ret;
85*12ea13adSMarek Vasut
86*12ea13adSMarek Vasut host->bus_hz = clk_get_rate(&clk);
87*12ea13adSMarek Vasut
88*12ea13adSMarek Vasut clk_free(&clk);
89*12ea13adSMarek Vasut #else
90*12ea13adSMarek Vasut /* Fixed clock divide by 4 which due to the SDMMC wrapper */
91*12ea13adSMarek Vasut host->bus_hz = cm_get_mmc_controller_clk_hz();
92*12ea13adSMarek Vasut #endif
93*12ea13adSMarek Vasut if (host->bus_hz == 0) {
94c35ed77aSMarek Vasut printf("DWMMC: MMC clock is zero!");
95498d1a62SPavel Machek return -EINVAL;
96498d1a62SPavel Machek }
9778606497SPavel Machek
98*12ea13adSMarek Vasut return 0;
99*12ea13adSMarek Vasut }
100*12ea13adSMarek Vasut
socfpga_dwmmc_ofdata_to_platdata(struct udevice * dev)101*12ea13adSMarek Vasut static int socfpga_dwmmc_ofdata_to_platdata(struct udevice *dev)
102*12ea13adSMarek Vasut {
103*12ea13adSMarek Vasut struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
104*12ea13adSMarek Vasut struct dwmci_host *host = &priv->host;
105*12ea13adSMarek Vasut int fifo_depth;
106*12ea13adSMarek Vasut
107e160f7d4SSimon Glass fifo_depth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
108c35ed77aSMarek Vasut "fifo-depth", 0);
109129adf5bSMarek Vasut if (fifo_depth < 0) {
110c35ed77aSMarek Vasut printf("DWMMC: Can't get FIFO depth\n");
111129adf5bSMarek Vasut return -EINVAL;
112129adf5bSMarek Vasut }
113129adf5bSMarek Vasut
114c35ed77aSMarek Vasut host->name = dev->name;
115a821c4afSSimon Glass host->ioaddr = (void *)devfdt_get_addr(dev);
116e160f7d4SSimon Glass host->buswidth = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
117c35ed77aSMarek Vasut "bus-width", 4);
118c5c1af21SChin Liang See host->clksel = socfpga_dwmci_clksel;
119c35ed77aSMarek Vasut
120c35ed77aSMarek Vasut /*
121c35ed77aSMarek Vasut * TODO(sjg@chromium.org): Remove the need for this hack.
122c35ed77aSMarek Vasut * We only have one dwmmc block on gen5 SoCFPGA.
123c35ed77aSMarek Vasut */
124c35ed77aSMarek Vasut host->dev_index = 0;
125c5c1af21SChin Liang See host->fifoth_val = MSIZE(0x2) |
126129adf5bSMarek Vasut RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
127e160f7d4SSimon Glass priv->drvsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
128c35ed77aSMarek Vasut "drvsel", 3);
129e160f7d4SSimon Glass priv->smplsel = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
130c35ed77aSMarek Vasut "smplsel", 0);
1319a41404dSChin Liang See host->priv = priv;
132c5c1af21SChin Liang See
133129adf5bSMarek Vasut return 0;
134129adf5bSMarek Vasut }
135129adf5bSMarek Vasut
socfpga_dwmmc_probe(struct udevice * dev)136c35ed77aSMarek Vasut static int socfpga_dwmmc_probe(struct udevice *dev)
137129adf5bSMarek Vasut {
138f1a485aaSSimon Glass #ifdef CONFIG_BLK
139f1a485aaSSimon Glass struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
140f1a485aaSSimon Glass #endif
141c35ed77aSMarek Vasut struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
142c35ed77aSMarek Vasut struct dwmci_socfpga_priv_data *priv = dev_get_priv(dev);
143c35ed77aSMarek Vasut struct dwmci_host *host = &priv->host;
144*12ea13adSMarek Vasut int ret;
145*12ea13adSMarek Vasut
146*12ea13adSMarek Vasut ret = socfpga_dwmmc_get_clk_rate(dev);
147*12ea13adSMarek Vasut if (ret)
148*12ea13adSMarek Vasut return ret;
149f1a485aaSSimon Glass
1502d4d6937SLey Foon Tan socfpga_dwmci_reset(dev);
1512d4d6937SLey Foon Tan
152f1a485aaSSimon Glass #ifdef CONFIG_BLK
153e5113c33SJaehoon Chung dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, 400000);
154f1a485aaSSimon Glass host->mmc = &plat->mmc;
155f1a485aaSSimon Glass #else
156129adf5bSMarek Vasut
157c35ed77aSMarek Vasut ret = add_dwmci(host, host->bus_hz, 400000);
158c35ed77aSMarek Vasut if (ret)
159129adf5bSMarek Vasut return ret;
160f1a485aaSSimon Glass #endif
161f1a485aaSSimon Glass host->mmc->priv = &priv->host;
162c35ed77aSMarek Vasut upriv->mmc = host->mmc;
163cffe5d86SSimon Glass host->mmc->dev = dev;
164c35ed77aSMarek Vasut
16555118ec9SPatrick Bruenn return dwmci_probe(dev);
166129adf5bSMarek Vasut }
167c35ed77aSMarek Vasut
socfpga_dwmmc_bind(struct udevice * dev)168f1a485aaSSimon Glass static int socfpga_dwmmc_bind(struct udevice *dev)
169f1a485aaSSimon Glass {
170f1a485aaSSimon Glass #ifdef CONFIG_BLK
171f1a485aaSSimon Glass struct socfpga_dwmci_plat *plat = dev_get_platdata(dev);
172f1a485aaSSimon Glass int ret;
173f1a485aaSSimon Glass
174f1a485aaSSimon Glass ret = dwmci_bind(dev, &plat->mmc, &plat->cfg);
175f1a485aaSSimon Glass if (ret)
176f1a485aaSSimon Glass return ret;
177f1a485aaSSimon Glass #endif
178f1a485aaSSimon Glass
179f1a485aaSSimon Glass return 0;
180f1a485aaSSimon Glass }
181f1a485aaSSimon Glass
182c35ed77aSMarek Vasut static const struct udevice_id socfpga_dwmmc_ids[] = {
183c35ed77aSMarek Vasut { .compatible = "altr,socfpga-dw-mshc" },
184c35ed77aSMarek Vasut { }
185c35ed77aSMarek Vasut };
186c35ed77aSMarek Vasut
187c35ed77aSMarek Vasut U_BOOT_DRIVER(socfpga_dwmmc_drv) = {
188c35ed77aSMarek Vasut .name = "socfpga_dwmmc",
189c35ed77aSMarek Vasut .id = UCLASS_MMC,
190c35ed77aSMarek Vasut .of_match = socfpga_dwmmc_ids,
191c35ed77aSMarek Vasut .ofdata_to_platdata = socfpga_dwmmc_ofdata_to_platdata,
192f55ae197SSylvain Lesne .ops = &dm_dwmci_ops,
193f1a485aaSSimon Glass .bind = socfpga_dwmmc_bind,
194c35ed77aSMarek Vasut .probe = socfpga_dwmmc_probe,
195c35ed77aSMarek Vasut .priv_auto_alloc_size = sizeof(struct dwmci_socfpga_priv_data),
196f55ae197SSylvain Lesne .platdata_auto_alloc_size = sizeof(struct socfpga_dwmci_plat),
197c35ed77aSMarek Vasut };
198