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Searched refs:dmc (Results 1 – 25 of 47) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c51 static void phy_control_reset(int ctrl_no, struct exynos4_dmc *dmc) in phy_control_reset() argument
55 &dmc->phycontrol1); in phy_control_reset()
57 &dmc->phycontrol1); in phy_control_reset()
60 &dmc->phycontrol0); in phy_control_reset()
62 &dmc->phycontrol0); in phy_control_reset()
66 static void dmc_config_mrs(struct exynos4_dmc *dmc, int chip) in dmc_config_mrs() argument
76 &dmc->directcmd); in dmc_config_mrs()
80 static void dmc_init(struct exynos4_dmc *dmc) in dmc_init() argument
87 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
94 writel(mem.zqcontrol, &dmc->phyzqcontrol); in dmc_init()
[all …]
H A Ddmc_init_ddr3.c39 struct exynos5_dmc *dmc; in ddr3_mem_ctrl_init() local
45 dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl(); in ddr3_mem_ctrl_init()
75 &dmc->concontrol); in ddr3_mem_ctrl_init()
77 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
102 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
105 &dmc->concontrol); in ddr3_mem_ctrl_init()
108 writel(mem->iv_size, &dmc->ivcontrol); in ddr3_mem_ctrl_init()
110 writel(mem->memconfig, &dmc->memconfig0); in ddr3_mem_ctrl_init()
111 writel(mem->memconfig, &dmc->memconfig1); in ddr3_mem_ctrl_init()
112 writel(mem->membaseconfig0, &dmc->membaseconfig0); in ddr3_mem_ctrl_init()
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3368-dmc.txt15 - compatible: "rockchip,rk3368-dmc"
54 #include <dt-bindings/memory/rk3368-dmc.h>
56 dmc: dmc@ff610000 {
58 compatible = "rockchip,rk3368-dmc";
63 &dmc {
H A Drockchip,rk3399-dmc.txt3 - compatible: "rockchip,rk3399-dmc", "syscon"
18 dmc: dmc {
20 compatible = "rockchip,rk3399-dmc";
35 &dmc {
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
18 -logic-supply: this driver should adjust VDD_LOGIC according to dmc frequency, so need get logic-su…
113 dmc: dmc@ff610000 {
114 compatible = "rockchip,rk3288-dmc", "syscon";
132 &dmc {
/openbmc/u-boot/drivers/ram/rockchip/
H A DMakefile6 obj-$(CONFIG_ROCKCHIP_RK3368) = dmc-rk3368.o
/openbmc/u-boot/arch/arm/dts/
H A Drk3368-lion-u-boot.dtsi28 &dmc {
41 * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
H A Drk3368-geekbox-u-boot.dtsi14 &dmc {
H A Drk3368-px5-evb-u-boot.dtsi14 &dmc {
H A Drk3368-sheep-u-boot.dtsi14 &dmc {
H A Drk3288-veyron-speedy-u-boot.dtsi6 &dmc {
H A Drk3288-vyasa-u-boot.dtsi6 &dmc {
H A Drk3288-miqi.dts18 &dmc {
H A Drk3288-evb.dts18 &dmc {
H A Drk3288-popmetal.dts18 &dmc {
H A Drk3288-fennec.dts18 &dmc {
H A Drk3288-tinker.dts18 &dmc {
H A Drk3288-firefly.dts23 &dmc {
H A Drk3229-evb.dts41 &dmc {
H A Drk3xxx.dtsi229 dmc: dmc@20020000 { label
231 compatible = "rockchip,rk3188-dmc", "syscon";
H A Dexynos5420-smdk5420.dts149 dmc {
H A Dexynos54xx.dtsi209 dmc {
H A Drk3288-veyron-jerry.dts69 &dmc {
H A Drk322x.dtsi772 dmc: dmc@11200000 { label
774 compatible = "rockchip,rk3228-dmc", "syscon";
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-graphics/tslib/
H A Dtslib_1.23.bb44 PACKAGECONFIG[dmc] = "--enable-dmc,--disable-dmc"

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