1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
277b55e8cSThomas Abraham /*
377b55e8cSThomas Abraham * DDR3 mem setup file for board based on EXYNOS5
477b55e8cSThomas Abraham *
577b55e8cSThomas Abraham * Copyright (C) 2012 Samsung Electronics
677b55e8cSThomas Abraham */
777b55e8cSThomas Abraham
877b55e8cSThomas Abraham #include <common.h>
977b55e8cSThomas Abraham #include <config.h>
1077b55e8cSThomas Abraham #include <asm/io.h>
1177b55e8cSThomas Abraham #include <asm/arch/clock.h>
1277b55e8cSThomas Abraham #include <asm/arch/cpu.h>
1377b55e8cSThomas Abraham #include <asm/arch/dmc.h>
1477b55e8cSThomas Abraham #include <asm/arch/power.h>
1577b55e8cSThomas Abraham #include "common_setup.h"
1677b55e8cSThomas Abraham #include "exynos5_setup.h"
1777b55e8cSThomas Abraham #include "clock_init.h"
1877b55e8cSThomas Abraham
1977b55e8cSThomas Abraham #define TIMEOUT_US 10000
2077b55e8cSThomas Abraham #define NUM_BYTE_LANES 4
2177b55e8cSThomas Abraham #define DEFAULT_DQS 8
2255a70c51SMinkyu Kang #define DEFAULT_DQS_X4 ((DEFAULT_DQS << 24) || (DEFAULT_DQS << 16) \
2355a70c51SMinkyu Kang || (DEFAULT_DQS << 8) || (DEFAULT_DQS << 0))
2477b55e8cSThomas Abraham
2577b55e8cSThomas Abraham #ifdef CONFIG_EXYNOS5250
reset_phy_ctrl(void)2677b55e8cSThomas Abraham static void reset_phy_ctrl(void)
2777b55e8cSThomas Abraham {
2877b55e8cSThomas Abraham struct exynos5_clock *clk =
2977b55e8cSThomas Abraham (struct exynos5_clock *)samsung_get_base_clock();
3077b55e8cSThomas Abraham
3177b55e8cSThomas Abraham writel(DDR3PHY_CTRL_PHY_RESET_OFF, &clk->lpddr3phy_ctrl);
3277b55e8cSThomas Abraham writel(DDR3PHY_CTRL_PHY_RESET, &clk->lpddr3phy_ctrl);
3377b55e8cSThomas Abraham }
3477b55e8cSThomas Abraham
ddr3_mem_ctrl_init(struct mem_timings * mem,int reset)3577b55e8cSThomas Abraham int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
3677b55e8cSThomas Abraham {
3777b55e8cSThomas Abraham unsigned int val;
3877b55e8cSThomas Abraham struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
3977b55e8cSThomas Abraham struct exynos5_dmc *dmc;
4077b55e8cSThomas Abraham int i;
4177b55e8cSThomas Abraham
4277b55e8cSThomas Abraham phy0_ctrl = (struct exynos5_phy_control *)samsung_get_base_dmc_phy();
4377b55e8cSThomas Abraham phy1_ctrl = (struct exynos5_phy_control *)(samsung_get_base_dmc_phy()
4477b55e8cSThomas Abraham + DMC_OFFSET);
4577b55e8cSThomas Abraham dmc = (struct exynos5_dmc *)samsung_get_base_dmc_ctrl();
4677b55e8cSThomas Abraham
4777b55e8cSThomas Abraham if (reset)
4877b55e8cSThomas Abraham reset_phy_ctrl();
4977b55e8cSThomas Abraham
5077b55e8cSThomas Abraham /* Set Impedance Output Driver */
5177b55e8cSThomas Abraham val = (mem->impedance << CA_CK_DRVR_DS_OFFSET) |
5277b55e8cSThomas Abraham (mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
5377b55e8cSThomas Abraham (mem->impedance << CA_CS_DRVR_DS_OFFSET) |
5477b55e8cSThomas Abraham (mem->impedance << CA_ADR_DRVR_DS_OFFSET);
5577b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con39);
5677b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con39);
5777b55e8cSThomas Abraham
5877b55e8cSThomas Abraham /* Set Read Latency and Burst Length for PHY0 and PHY1 */
5977b55e8cSThomas Abraham val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
6077b55e8cSThomas Abraham (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
6177b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con42);
6277b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con42);
6377b55e8cSThomas Abraham
6477b55e8cSThomas Abraham /* ZQ Calibration */
6577b55e8cSThomas Abraham if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
6677b55e8cSThomas Abraham &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
6777b55e8cSThomas Abraham return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
6877b55e8cSThomas Abraham
6977b55e8cSThomas Abraham /* DQ Signal */
7077b55e8cSThomas Abraham writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
7177b55e8cSThomas Abraham writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
7277b55e8cSThomas Abraham
7377b55e8cSThomas Abraham writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
7477b55e8cSThomas Abraham | (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
7577b55e8cSThomas Abraham &dmc->concontrol);
7677b55e8cSThomas Abraham
7777b55e8cSThomas Abraham update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
7877b55e8cSThomas Abraham
7977b55e8cSThomas Abraham /* DQS Signal */
8077b55e8cSThomas Abraham writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
8177b55e8cSThomas Abraham writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
8277b55e8cSThomas Abraham
8377b55e8cSThomas Abraham writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
8477b55e8cSThomas Abraham writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
8577b55e8cSThomas Abraham
8677b55e8cSThomas Abraham writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
8777b55e8cSThomas Abraham writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
8877b55e8cSThomas Abraham
8977b55e8cSThomas Abraham val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
9077b55e8cSThomas Abraham (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
9177b55e8cSThomas Abraham (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
9277b55e8cSThomas Abraham (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
9377b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con12);
9477b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con12);
9577b55e8cSThomas Abraham
9677b55e8cSThomas Abraham /* Start DLL locking */
9777b55e8cSThomas Abraham writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
9877b55e8cSThomas Abraham &phy0_ctrl->phy_con12);
9977b55e8cSThomas Abraham writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
10077b55e8cSThomas Abraham &phy1_ctrl->phy_con12);
10177b55e8cSThomas Abraham
10277b55e8cSThomas Abraham update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
10377b55e8cSThomas Abraham
10477b55e8cSThomas Abraham writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
10577b55e8cSThomas Abraham &dmc->concontrol);
10677b55e8cSThomas Abraham
10777b55e8cSThomas Abraham /* Memory Channel Inteleaving Size */
10877b55e8cSThomas Abraham writel(mem->iv_size, &dmc->ivcontrol);
10977b55e8cSThomas Abraham
11077b55e8cSThomas Abraham writel(mem->memconfig, &dmc->memconfig0);
11177b55e8cSThomas Abraham writel(mem->memconfig, &dmc->memconfig1);
11277b55e8cSThomas Abraham writel(mem->membaseconfig0, &dmc->membaseconfig0);
11377b55e8cSThomas Abraham writel(mem->membaseconfig1, &dmc->membaseconfig1);
11477b55e8cSThomas Abraham
11577b55e8cSThomas Abraham /* Precharge Configuration */
11677b55e8cSThomas Abraham writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
11777b55e8cSThomas Abraham &dmc->prechconfig);
11877b55e8cSThomas Abraham
11977b55e8cSThomas Abraham /* Power Down mode Configuration */
12077b55e8cSThomas Abraham writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
12177b55e8cSThomas Abraham mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
12277b55e8cSThomas Abraham &dmc->pwrdnconfig);
12377b55e8cSThomas Abraham
12477b55e8cSThomas Abraham /* TimingRow, TimingData, TimingPower and Timingaref
12577b55e8cSThomas Abraham * values as per Memory AC parameters
12677b55e8cSThomas Abraham */
12777b55e8cSThomas Abraham writel(mem->timing_ref, &dmc->timingref);
12877b55e8cSThomas Abraham writel(mem->timing_row, &dmc->timingrow);
12977b55e8cSThomas Abraham writel(mem->timing_data, &dmc->timingdata);
13077b55e8cSThomas Abraham writel(mem->timing_power, &dmc->timingpower);
13177b55e8cSThomas Abraham
13277b55e8cSThomas Abraham /* Send PALL command */
13377b55e8cSThomas Abraham dmc_config_prech(mem, &dmc->directcmd);
13477b55e8cSThomas Abraham
13577b55e8cSThomas Abraham /* Send NOP, MRS and ZQINIT commands */
13677b55e8cSThomas Abraham dmc_config_mrs(mem, &dmc->directcmd);
13777b55e8cSThomas Abraham
13877b55e8cSThomas Abraham if (mem->gate_leveling_enable) {
13977b55e8cSThomas Abraham val = PHY_CON0_RESET_VAL;
14077b55e8cSThomas Abraham val |= P0_CMD_EN;
14177b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con0);
14277b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con0);
14377b55e8cSThomas Abraham
14477b55e8cSThomas Abraham val = PHY_CON2_RESET_VAL;
14577b55e8cSThomas Abraham val |= INIT_DESKEW_EN;
14677b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con2);
14777b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con2);
14877b55e8cSThomas Abraham
14977b55e8cSThomas Abraham val = PHY_CON0_RESET_VAL;
15077b55e8cSThomas Abraham val |= P0_CMD_EN;
15177b55e8cSThomas Abraham val |= BYTE_RDLVL_EN;
15277b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con0);
15377b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con0);
15477b55e8cSThomas Abraham
15577b55e8cSThomas Abraham val = (mem->ctrl_start_point <<
15677b55e8cSThomas Abraham PHY_CON12_CTRL_START_POINT_SHIFT) |
15777b55e8cSThomas Abraham (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
15877b55e8cSThomas Abraham (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
15977b55e8cSThomas Abraham (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
16077b55e8cSThomas Abraham (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
16177b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con12);
16277b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con12);
16377b55e8cSThomas Abraham
16477b55e8cSThomas Abraham val = PHY_CON2_RESET_VAL;
16577b55e8cSThomas Abraham val |= INIT_DESKEW_EN;
16677b55e8cSThomas Abraham val |= RDLVL_GATE_EN;
16777b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con2);
16877b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con2);
16977b55e8cSThomas Abraham
17077b55e8cSThomas Abraham val = PHY_CON0_RESET_VAL;
17177b55e8cSThomas Abraham val |= P0_CMD_EN;
17277b55e8cSThomas Abraham val |= BYTE_RDLVL_EN;
17377b55e8cSThomas Abraham val |= CTRL_SHGATE;
17477b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con0);
17577b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con0);
17677b55e8cSThomas Abraham
17777b55e8cSThomas Abraham val = PHY_CON1_RESET_VAL;
17877b55e8cSThomas Abraham val &= ~(CTRL_GATEDURADJ_MASK);
17977b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con1);
18077b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con1);
18177b55e8cSThomas Abraham
18277b55e8cSThomas Abraham writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
18377b55e8cSThomas Abraham i = TIMEOUT_US;
18477b55e8cSThomas Abraham while ((readl(&dmc->phystatus) &
18577b55e8cSThomas Abraham (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
18677b55e8cSThomas Abraham (RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
18777b55e8cSThomas Abraham /*
18877b55e8cSThomas Abraham * TODO(waihong): Comment on how long this take to
18977b55e8cSThomas Abraham * timeout
19077b55e8cSThomas Abraham */
19177b55e8cSThomas Abraham sdelay(100);
19277b55e8cSThomas Abraham i--;
19377b55e8cSThomas Abraham }
19477b55e8cSThomas Abraham if (!i)
19577b55e8cSThomas Abraham return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
19677b55e8cSThomas Abraham writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
19777b55e8cSThomas Abraham
19877b55e8cSThomas Abraham writel(0, &phy0_ctrl->phy_con14);
19977b55e8cSThomas Abraham writel(0, &phy1_ctrl->phy_con14);
20077b55e8cSThomas Abraham
20177b55e8cSThomas Abraham val = (mem->ctrl_start_point <<
20277b55e8cSThomas Abraham PHY_CON12_CTRL_START_POINT_SHIFT) |
20377b55e8cSThomas Abraham (mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
20477b55e8cSThomas Abraham (mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
20577b55e8cSThomas Abraham (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
20677b55e8cSThomas Abraham (mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
20777b55e8cSThomas Abraham (mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
20877b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con12);
20977b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con12);
21077b55e8cSThomas Abraham
21177b55e8cSThomas Abraham update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3);
21277b55e8cSThomas Abraham }
21377b55e8cSThomas Abraham
21477b55e8cSThomas Abraham /* Send PALL command */
21577b55e8cSThomas Abraham dmc_config_prech(mem, &dmc->directcmd);
21677b55e8cSThomas Abraham
21777b55e8cSThomas Abraham writel(mem->memcontrol, &dmc->memcontrol);
21877b55e8cSThomas Abraham
21977b55e8cSThomas Abraham /* Set DMC Concontrol and enable auto-refresh counter */
22077b55e8cSThomas Abraham writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
22177b55e8cSThomas Abraham | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
22277b55e8cSThomas Abraham return 0;
22377b55e8cSThomas Abraham }
22477b55e8cSThomas Abraham #endif
22577b55e8cSThomas Abraham
22677b55e8cSThomas Abraham #ifdef CONFIG_EXYNOS5420
22777b55e8cSThomas Abraham /**
22877b55e8cSThomas Abraham * RAM address to use in the test.
22977b55e8cSThomas Abraham *
23077b55e8cSThomas Abraham * We'll use 4 words at this address and 4 at this address + 0x80 (Ares
23177b55e8cSThomas Abraham * interleaves channels every 128 bytes). This will allow us to evaluate all of
23277b55e8cSThomas Abraham * the chips in a 1 chip per channel (2GB) system and half the chips in a 2
23377b55e8cSThomas Abraham * chip per channel (4GB) system. We can't test the 2nd chip since we need to
23477b55e8cSThomas Abraham * do tests before the 2nd chip is enabled. Looking at the 2nd chip isn't
23577b55e8cSThomas Abraham * critical because the 1st and 2nd chip have very similar timings (they'd
23677b55e8cSThomas Abraham * better have similar timings, since there's only a single adjustment that is
23777b55e8cSThomas Abraham * shared by both chips).
23877b55e8cSThomas Abraham */
23977b55e8cSThomas Abraham const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE;
24077b55e8cSThomas Abraham
24177b55e8cSThomas Abraham /* Test pattern with which RAM will be tested */
24277b55e8cSThomas Abraham static const unsigned int test_pattern[] = {
24377b55e8cSThomas Abraham 0x5a5a5a5a,
24477b55e8cSThomas Abraham 0xa5a5a5a5,
24577b55e8cSThomas Abraham 0xf0f0f0f0,
24677b55e8cSThomas Abraham 0x0f0f0f0f,
24777b55e8cSThomas Abraham };
24877b55e8cSThomas Abraham
24977b55e8cSThomas Abraham /**
25077b55e8cSThomas Abraham * This function is a test vector for sw read leveling,
25177b55e8cSThomas Abraham * it compares the read data with the written data.
25277b55e8cSThomas Abraham *
25377b55e8cSThomas Abraham * @param ch DMC channel number
25477b55e8cSThomas Abraham * @param byte_lane which DQS byte offset,
25577b55e8cSThomas Abraham * possible values are 0,1,2,3
25677b55e8cSThomas Abraham * @return TRUE if memory was good, FALSE if not.
25777b55e8cSThomas Abraham */
dmc_valid_window_test_vector(int ch,int byte_lane)25877b55e8cSThomas Abraham static bool dmc_valid_window_test_vector(int ch, int byte_lane)
25977b55e8cSThomas Abraham {
26077b55e8cSThomas Abraham unsigned int read_data;
26177b55e8cSThomas Abraham unsigned int mask;
26277b55e8cSThomas Abraham int i;
26377b55e8cSThomas Abraham
26477b55e8cSThomas Abraham mask = 0xFF << (8 * byte_lane);
26577b55e8cSThomas Abraham
26677b55e8cSThomas Abraham for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
26777b55e8cSThomas Abraham read_data = readl(test_addr + i * 4 + ch * 0x80);
26877b55e8cSThomas Abraham if ((read_data & mask) != (test_pattern[i] & mask))
26977b55e8cSThomas Abraham return false;
27077b55e8cSThomas Abraham }
27177b55e8cSThomas Abraham
27277b55e8cSThomas Abraham return true;
27377b55e8cSThomas Abraham }
27477b55e8cSThomas Abraham
27577b55e8cSThomas Abraham /**
27677b55e8cSThomas Abraham * This function returns current read offset value.
27777b55e8cSThomas Abraham *
27877b55e8cSThomas Abraham * @param phy_ctrl pointer to the current phy controller
27977b55e8cSThomas Abraham */
dmc_get_read_offset_value(struct exynos5420_phy_control * phy_ctrl)28077b55e8cSThomas Abraham static unsigned int dmc_get_read_offset_value(struct exynos5420_phy_control
28177b55e8cSThomas Abraham *phy_ctrl)
28277b55e8cSThomas Abraham {
28377b55e8cSThomas Abraham return readl(&phy_ctrl->phy_con4);
28477b55e8cSThomas Abraham }
28577b55e8cSThomas Abraham
28677b55e8cSThomas Abraham /**
28777b55e8cSThomas Abraham * This function performs resync, so that slave DLL is updated.
28877b55e8cSThomas Abraham *
28977b55e8cSThomas Abraham * @param phy_ctrl pointer to the current phy controller
29077b55e8cSThomas Abraham */
ddr_phy_set_do_resync(struct exynos5420_phy_control * phy_ctrl)29177b55e8cSThomas Abraham static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl)
29277b55e8cSThomas Abraham {
29377b55e8cSThomas Abraham setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
29477b55e8cSThomas Abraham clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3);
29577b55e8cSThomas Abraham }
29677b55e8cSThomas Abraham
29777b55e8cSThomas Abraham /**
29877b55e8cSThomas Abraham * This function sets read offset value register with 'offset'.
29977b55e8cSThomas Abraham *
30077b55e8cSThomas Abraham * ...we also call call ddr_phy_set_do_resync().
30177b55e8cSThomas Abraham *
30277b55e8cSThomas Abraham * @param phy_ctrl pointer to the current phy controller
30377b55e8cSThomas Abraham * @param offset offset to read DQS
30477b55e8cSThomas Abraham */
dmc_set_read_offset_value(struct exynos5420_phy_control * phy_ctrl,unsigned int offset)30577b55e8cSThomas Abraham static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl,
30677b55e8cSThomas Abraham unsigned int offset)
30777b55e8cSThomas Abraham {
30877b55e8cSThomas Abraham writel(offset, &phy_ctrl->phy_con4);
30977b55e8cSThomas Abraham ddr_phy_set_do_resync(phy_ctrl);
31077b55e8cSThomas Abraham }
31177b55e8cSThomas Abraham
31277b55e8cSThomas Abraham /**
31377b55e8cSThomas Abraham * Convert a 2s complement byte to a byte with a sign bit.
31477b55e8cSThomas Abraham *
31577b55e8cSThomas Abraham * NOTE: you shouldn't use normal math on the number returned by this function.
31677b55e8cSThomas Abraham * As an example, -10 = 0xf6. After this function -10 = 0x8a. If you wanted
31777b55e8cSThomas Abraham * to do math and get the average of 10 and -10 (should be 0):
31877b55e8cSThomas Abraham * 0x8a + 0xa = 0x94 (-108)
31977b55e8cSThomas Abraham * 0x94 / 2 = 0xca (-54)
32077b55e8cSThomas Abraham * ...and 0xca = sign bit plus 0x4a, or -74
32177b55e8cSThomas Abraham *
32277b55e8cSThomas Abraham * Also note that you lose the ability to represent -128 since there are two
32377b55e8cSThomas Abraham * representations of 0.
32477b55e8cSThomas Abraham *
32577b55e8cSThomas Abraham * @param b The byte to convert in two's complement.
32677b55e8cSThomas Abraham * @return The 7-bit value + sign bit.
32777b55e8cSThomas Abraham */
32877b55e8cSThomas Abraham
make_signed_byte(signed char b)32977b55e8cSThomas Abraham unsigned char make_signed_byte(signed char b)
33077b55e8cSThomas Abraham {
33177b55e8cSThomas Abraham if (b < 0)
33277b55e8cSThomas Abraham return 0x80 | -b;
33377b55e8cSThomas Abraham else
33477b55e8cSThomas Abraham return b;
33577b55e8cSThomas Abraham }
33677b55e8cSThomas Abraham
33777b55e8cSThomas Abraham /**
33877b55e8cSThomas Abraham * Test various shifts starting at 'start' and going to 'end'.
33977b55e8cSThomas Abraham *
34077b55e8cSThomas Abraham * For each byte lane, we'll walk through shift starting at 'start' and going
34177b55e8cSThomas Abraham * to 'end' (inclusive). When we are finally able to read the test pattern
34277b55e8cSThomas Abraham * we'll store the value in the results array.
34377b55e8cSThomas Abraham *
34477b55e8cSThomas Abraham * @param phy_ctrl pointer to the current phy controller
34577b55e8cSThomas Abraham * @param ch channel number
34677b55e8cSThomas Abraham * @param start the start shift. -127 to 127
34777b55e8cSThomas Abraham * @param end the end shift. -127 to 127
34877b55e8cSThomas Abraham * @param results we'll store results for each byte lane.
34977b55e8cSThomas Abraham */
35077b55e8cSThomas Abraham
test_shifts(struct exynos5420_phy_control * phy_ctrl,int ch,int start,int end,int results[NUM_BYTE_LANES])35177b55e8cSThomas Abraham void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch,
35277b55e8cSThomas Abraham int start, int end, int results[NUM_BYTE_LANES])
35377b55e8cSThomas Abraham {
35477b55e8cSThomas Abraham int incr = (start < end) ? 1 : -1;
35577b55e8cSThomas Abraham int byte_lane;
35677b55e8cSThomas Abraham
35777b55e8cSThomas Abraham for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
35877b55e8cSThomas Abraham int shift;
35977b55e8cSThomas Abraham
36077b55e8cSThomas Abraham dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4);
36177b55e8cSThomas Abraham results[byte_lane] = DEFAULT_DQS;
36277b55e8cSThomas Abraham
36377b55e8cSThomas Abraham for (shift = start; shift != (end + incr); shift += incr) {
36477b55e8cSThomas Abraham unsigned int byte_offsetr;
36577b55e8cSThomas Abraham unsigned int offsetr;
36677b55e8cSThomas Abraham
36777b55e8cSThomas Abraham byte_offsetr = make_signed_byte(shift);
36877b55e8cSThomas Abraham
36977b55e8cSThomas Abraham offsetr = dmc_get_read_offset_value(phy_ctrl);
37077b55e8cSThomas Abraham offsetr &= ~(0xFF << (8 * byte_lane));
37177b55e8cSThomas Abraham offsetr |= (byte_offsetr << (8 * byte_lane));
37277b55e8cSThomas Abraham dmc_set_read_offset_value(phy_ctrl, offsetr);
37377b55e8cSThomas Abraham
37477b55e8cSThomas Abraham if (dmc_valid_window_test_vector(ch, byte_lane)) {
37577b55e8cSThomas Abraham results[byte_lane] = shift;
37677b55e8cSThomas Abraham break;
37777b55e8cSThomas Abraham }
37877b55e8cSThomas Abraham }
37977b55e8cSThomas Abraham }
38077b55e8cSThomas Abraham }
38177b55e8cSThomas Abraham
38277b55e8cSThomas Abraham /**
38377b55e8cSThomas Abraham * This function performs SW read leveling to compensate DQ-DQS skew at
38477b55e8cSThomas Abraham * receiver it first finds the optimal read offset value on each DQS
38577b55e8cSThomas Abraham * then applies the value to PHY.
38677b55e8cSThomas Abraham *
38777b55e8cSThomas Abraham * Read offset value has its min margin and max margin. If read offset
38877b55e8cSThomas Abraham * value exceeds its min or max margin, read data will have corruption.
38977b55e8cSThomas Abraham * To avoid this we are doing sw read leveling.
39077b55e8cSThomas Abraham *
39177b55e8cSThomas Abraham * SW read leveling is:
39277b55e8cSThomas Abraham * 1> Finding offset value's left_limit and right_limit
39377b55e8cSThomas Abraham * 2> and calculate its center value
39477b55e8cSThomas Abraham * 3> finally programs that center value to PHY
39577b55e8cSThomas Abraham * 4> then PHY gets its optimal offset value.
39677b55e8cSThomas Abraham *
39777b55e8cSThomas Abraham * @param phy_ctrl pointer to the current phy controller
39877b55e8cSThomas Abraham * @param ch channel number
39977b55e8cSThomas Abraham * @param coarse_lock_val The coarse lock value read from PHY_CON13.
40077b55e8cSThomas Abraham * (0 - 0x7f)
40177b55e8cSThomas Abraham */
software_find_read_offset(struct exynos5420_phy_control * phy_ctrl,int ch,unsigned int coarse_lock_val)40277b55e8cSThomas Abraham static void software_find_read_offset(struct exynos5420_phy_control *phy_ctrl,
40377b55e8cSThomas Abraham int ch, unsigned int coarse_lock_val)
40477b55e8cSThomas Abraham {
40577b55e8cSThomas Abraham unsigned int offsetr_cent;
40677b55e8cSThomas Abraham int byte_lane;
40777b55e8cSThomas Abraham int left_limit;
40877b55e8cSThomas Abraham int right_limit;
40977b55e8cSThomas Abraham int left[NUM_BYTE_LANES];
41077b55e8cSThomas Abraham int right[NUM_BYTE_LANES];
41177b55e8cSThomas Abraham int i;
41277b55e8cSThomas Abraham
41377b55e8cSThomas Abraham /* Fill the memory with test patterns */
41477b55e8cSThomas Abraham for (i = 0; i < ARRAY_SIZE(test_pattern); i++)
41577b55e8cSThomas Abraham writel(test_pattern[i], test_addr + i * 4 + ch * 0x80);
41677b55e8cSThomas Abraham
41777b55e8cSThomas Abraham /* Figure out the limits we'll test with; keep -127 < limit < 127 */
41877b55e8cSThomas Abraham left_limit = DEFAULT_DQS - coarse_lock_val;
41977b55e8cSThomas Abraham right_limit = DEFAULT_DQS + coarse_lock_val;
42077b55e8cSThomas Abraham if (right_limit > 127)
42177b55e8cSThomas Abraham right_limit = 127;
42277b55e8cSThomas Abraham
42377b55e8cSThomas Abraham /* Fill in the location where reads were OK from left and right */
42477b55e8cSThomas Abraham test_shifts(phy_ctrl, ch, left_limit, right_limit, left);
42577b55e8cSThomas Abraham test_shifts(phy_ctrl, ch, right_limit, left_limit, right);
42677b55e8cSThomas Abraham
42777b55e8cSThomas Abraham /* Make a final value by taking the center between the left and right */
42877b55e8cSThomas Abraham offsetr_cent = 0;
42977b55e8cSThomas Abraham for (byte_lane = 0; byte_lane < NUM_BYTE_LANES; byte_lane++) {
43077b55e8cSThomas Abraham int temp_center;
43177b55e8cSThomas Abraham unsigned int vmwc;
43277b55e8cSThomas Abraham
43377b55e8cSThomas Abraham temp_center = (left[byte_lane] + right[byte_lane]) / 2;
43477b55e8cSThomas Abraham vmwc = make_signed_byte(temp_center);
43577b55e8cSThomas Abraham offsetr_cent |= vmwc << (8 * byte_lane);
43677b55e8cSThomas Abraham }
43777b55e8cSThomas Abraham dmc_set_read_offset_value(phy_ctrl, offsetr_cent);
43877b55e8cSThomas Abraham }
43977b55e8cSThomas Abraham
ddr3_mem_ctrl_init(struct mem_timings * mem,int reset)44077b55e8cSThomas Abraham int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
44177b55e8cSThomas Abraham {
44277b55e8cSThomas Abraham struct exynos5420_clock *clk =
44377b55e8cSThomas Abraham (struct exynos5420_clock *)samsung_get_base_clock();
44477b55e8cSThomas Abraham struct exynos5420_power *power =
44577b55e8cSThomas Abraham (struct exynos5420_power *)samsung_get_base_power();
44677b55e8cSThomas Abraham struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
44777b55e8cSThomas Abraham struct exynos5420_dmc *drex0, *drex1;
44877b55e8cSThomas Abraham struct exynos5420_tzasc *tzasc0, *tzasc1;
44977b55e8cSThomas Abraham struct exynos5_power *pmu;
45077b55e8cSThomas Abraham uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
45177b55e8cSThomas Abraham uint32_t lock0_info, lock1_info;
45277b55e8cSThomas Abraham int chip;
45377b55e8cSThomas Abraham int i;
45477b55e8cSThomas Abraham
45577b55e8cSThomas Abraham phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
45677b55e8cSThomas Abraham phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
45777b55e8cSThomas Abraham + DMC_OFFSET);
45877b55e8cSThomas Abraham drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
45977b55e8cSThomas Abraham drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
46077b55e8cSThomas Abraham + DMC_OFFSET);
46177b55e8cSThomas Abraham tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
46277b55e8cSThomas Abraham tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
46377b55e8cSThomas Abraham + DMC_OFFSET);
46477b55e8cSThomas Abraham pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
46577b55e8cSThomas Abraham
46677b55e8cSThomas Abraham if (CONFIG_NR_DRAM_BANKS > 4) {
46777b55e8cSThomas Abraham /* Need both controllers. */
46877b55e8cSThomas Abraham mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
46977b55e8cSThomas Abraham mem->chips_per_channel = 2;
47077b55e8cSThomas Abraham mem->chips_to_configure = 2;
47177b55e8cSThomas Abraham } else {
47277b55e8cSThomas Abraham /* 2GB requires a single controller */
47377b55e8cSThomas Abraham mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
47477b55e8cSThomas Abraham }
47577b55e8cSThomas Abraham
47677b55e8cSThomas Abraham /* Enable PAUSE for DREX */
47777b55e8cSThomas Abraham setbits_le32(&clk->pause, ENABLE_BIT);
47877b55e8cSThomas Abraham
47977b55e8cSThomas Abraham /* Enable BYPASS mode */
48077b55e8cSThomas Abraham setbits_le32(&clk->bpll_con1, BYPASS_EN);
48177b55e8cSThomas Abraham
48277b55e8cSThomas Abraham writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
48377b55e8cSThomas Abraham do {
48477b55e8cSThomas Abraham val = readl(&clk->mux_stat_cdrex);
48577b55e8cSThomas Abraham val &= BPLL_SEL_MASK;
48677b55e8cSThomas Abraham } while (val != FOUTBPLL);
48777b55e8cSThomas Abraham
48877b55e8cSThomas Abraham clrbits_le32(&clk->bpll_con1, BYPASS_EN);
48977b55e8cSThomas Abraham
49077b55e8cSThomas Abraham /* Specify the DDR memory type as DDR3 */
49177b55e8cSThomas Abraham val = readl(&phy0_ctrl->phy_con0);
49277b55e8cSThomas Abraham val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
49377b55e8cSThomas Abraham val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
49477b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con0);
49577b55e8cSThomas Abraham
49677b55e8cSThomas Abraham val = readl(&phy1_ctrl->phy_con0);
49777b55e8cSThomas Abraham val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
49877b55e8cSThomas Abraham val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
49977b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con0);
50077b55e8cSThomas Abraham
50177b55e8cSThomas Abraham /* Set Read Latency and Burst Length for PHY0 and PHY1 */
50277b55e8cSThomas Abraham val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
50377b55e8cSThomas Abraham (mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
50477b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con42);
50577b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con42);
50677b55e8cSThomas Abraham
50777b55e8cSThomas Abraham val = readl(&phy0_ctrl->phy_con26);
50877b55e8cSThomas Abraham val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
50977b55e8cSThomas Abraham val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
51077b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con26);
51177b55e8cSThomas Abraham
51277b55e8cSThomas Abraham val = readl(&phy1_ctrl->phy_con26);
51377b55e8cSThomas Abraham val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
51477b55e8cSThomas Abraham val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
51577b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con26);
51677b55e8cSThomas Abraham
51777b55e8cSThomas Abraham /*
51877b55e8cSThomas Abraham * Set Driver strength for CK, CKE, CS & CA to 0x7
51977b55e8cSThomas Abraham * Set Driver strength for Data Slice 0~3 to 0x7
52077b55e8cSThomas Abraham */
52177b55e8cSThomas Abraham val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
52277b55e8cSThomas Abraham (0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
52377b55e8cSThomas Abraham val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
52477b55e8cSThomas Abraham (0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
52577b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con39);
52677b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con39);
52777b55e8cSThomas Abraham
52877b55e8cSThomas Abraham /* ZQ Calibration */
52977b55e8cSThomas Abraham if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
53077b55e8cSThomas Abraham &phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
53177b55e8cSThomas Abraham return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
53277b55e8cSThomas Abraham
53377b55e8cSThomas Abraham clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
53477b55e8cSThomas Abraham clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
53577b55e8cSThomas Abraham
53677b55e8cSThomas Abraham /* DQ Signal */
53777b55e8cSThomas Abraham val = readl(&phy0_ctrl->phy_con14);
53877b55e8cSThomas Abraham val |= mem->phy0_pulld_dqs;
53977b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con14);
54077b55e8cSThomas Abraham val = readl(&phy1_ctrl->phy_con14);
54177b55e8cSThomas Abraham val |= mem->phy1_pulld_dqs;
54277b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con14);
54377b55e8cSThomas Abraham
54477b55e8cSThomas Abraham val = MEM_TERM_EN | PHY_TERM_EN;
54577b55e8cSThomas Abraham writel(val, &drex0->phycontrol0);
54677b55e8cSThomas Abraham writel(val, &drex1->phycontrol0);
54777b55e8cSThomas Abraham
54877b55e8cSThomas Abraham writel(mem->concontrol |
54977b55e8cSThomas Abraham (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
55077b55e8cSThomas Abraham (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
55177b55e8cSThomas Abraham &drex0->concontrol);
55277b55e8cSThomas Abraham writel(mem->concontrol |
55377b55e8cSThomas Abraham (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
55477b55e8cSThomas Abraham (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
55577b55e8cSThomas Abraham &drex1->concontrol);
55677b55e8cSThomas Abraham
55777b55e8cSThomas Abraham do {
55877b55e8cSThomas Abraham val = readl(&drex0->phystatus);
55977b55e8cSThomas Abraham } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
56077b55e8cSThomas Abraham do {
56177b55e8cSThomas Abraham val = readl(&drex1->phystatus);
56277b55e8cSThomas Abraham } while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
56377b55e8cSThomas Abraham
56477b55e8cSThomas Abraham clrbits_le32(&drex0->concontrol, DFI_INIT_START);
56577b55e8cSThomas Abraham clrbits_le32(&drex1->concontrol, DFI_INIT_START);
56677b55e8cSThomas Abraham
56777b55e8cSThomas Abraham update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
56877b55e8cSThomas Abraham update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
56977b55e8cSThomas Abraham
57077b55e8cSThomas Abraham /*
57177b55e8cSThomas Abraham * Set Base Address:
57277b55e8cSThomas Abraham * 0x2000_0000 ~ 0x5FFF_FFFF
57377b55e8cSThomas Abraham * 0x6000_0000 ~ 0x9FFF_FFFF
57477b55e8cSThomas Abraham */
57577b55e8cSThomas Abraham /* MEMBASECONFIG0 */
57677b55e8cSThomas Abraham val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
57777b55e8cSThomas Abraham DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
57877b55e8cSThomas Abraham writel(val, &tzasc0->membaseconfig0);
57977b55e8cSThomas Abraham writel(val, &tzasc1->membaseconfig0);
58077b55e8cSThomas Abraham
58177b55e8cSThomas Abraham /* MEMBASECONFIG1 */
58277b55e8cSThomas Abraham val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
58377b55e8cSThomas Abraham DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
58477b55e8cSThomas Abraham writel(val, &tzasc0->membaseconfig1);
58577b55e8cSThomas Abraham writel(val, &tzasc1->membaseconfig1);
58677b55e8cSThomas Abraham
58777b55e8cSThomas Abraham /*
58877b55e8cSThomas Abraham * Memory Channel Inteleaving Size
58977b55e8cSThomas Abraham * Ares Channel interleaving = 128 bytes
59077b55e8cSThomas Abraham */
59177b55e8cSThomas Abraham /* MEMCONFIG0/1 */
59277b55e8cSThomas Abraham writel(mem->memconfig, &tzasc0->memconfig0);
59377b55e8cSThomas Abraham writel(mem->memconfig, &tzasc1->memconfig0);
59477b55e8cSThomas Abraham writel(mem->memconfig, &tzasc0->memconfig1);
59577b55e8cSThomas Abraham writel(mem->memconfig, &tzasc1->memconfig1);
59677b55e8cSThomas Abraham
59777b55e8cSThomas Abraham /* Precharge Configuration */
59877b55e8cSThomas Abraham writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
59977b55e8cSThomas Abraham &drex0->prechconfig0);
60077b55e8cSThomas Abraham writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
60177b55e8cSThomas Abraham &drex1->prechconfig0);
60277b55e8cSThomas Abraham
60377b55e8cSThomas Abraham /*
60477b55e8cSThomas Abraham * TimingRow, TimingData, TimingPower and Timingaref
60577b55e8cSThomas Abraham * values as per Memory AC parameters
60677b55e8cSThomas Abraham */
60777b55e8cSThomas Abraham writel(mem->timing_ref, &drex0->timingref);
60877b55e8cSThomas Abraham writel(mem->timing_ref, &drex1->timingref);
60977b55e8cSThomas Abraham writel(mem->timing_row, &drex0->timingrow0);
61077b55e8cSThomas Abraham writel(mem->timing_row, &drex1->timingrow0);
61177b55e8cSThomas Abraham writel(mem->timing_data, &drex0->timingdata0);
61277b55e8cSThomas Abraham writel(mem->timing_data, &drex1->timingdata0);
61377b55e8cSThomas Abraham writel(mem->timing_power, &drex0->timingpower0);
61477b55e8cSThomas Abraham writel(mem->timing_power, &drex1->timingpower0);
61577b55e8cSThomas Abraham
61677b55e8cSThomas Abraham if (reset) {
61777b55e8cSThomas Abraham /*
61877b55e8cSThomas Abraham * Send NOP, MRS and ZQINIT commands
61977b55e8cSThomas Abraham * Sending MRS command will reset the DRAM. We should not be
6203450a859SVagrant Cascadian * resetting the DRAM after resume, this will lead to memory
62177b55e8cSThomas Abraham * corruption as DRAM content is lost after DRAM reset
62277b55e8cSThomas Abraham */
62377b55e8cSThomas Abraham dmc_config_mrs(mem, &drex0->directcmd);
62477b55e8cSThomas Abraham dmc_config_mrs(mem, &drex1->directcmd);
62577b55e8cSThomas Abraham }
62677b55e8cSThomas Abraham
62777b55e8cSThomas Abraham /*
62877b55e8cSThomas Abraham * Get PHY_CON13 from both phys. Gate CLKM around reading since
62977b55e8cSThomas Abraham * PHY_CON13 is glitchy when CLKM is running. We're paranoid and
63077b55e8cSThomas Abraham * wait until we get a "fine lock", though a coarse lock is probably
63177b55e8cSThomas Abraham * OK (we only use the coarse numbers below). We try to gate the
63277b55e8cSThomas Abraham * clock for as short a time as possible in case SDRAM is somehow
63377b55e8cSThomas Abraham * sensitive. sdelay(10) in the loop is arbitrary to make sure
63477b55e8cSThomas Abraham * there is some time for PHY_CON13 to get updated. In practice
63577b55e8cSThomas Abraham * no delay appears to be needed.
63677b55e8cSThomas Abraham */
63777b55e8cSThomas Abraham val = readl(&clk->gate_bus_cdrex);
63877b55e8cSThomas Abraham while (true) {
63977b55e8cSThomas Abraham writel(val & ~0x1, &clk->gate_bus_cdrex);
64077b55e8cSThomas Abraham lock0_info = readl(&phy0_ctrl->phy_con13);
64177b55e8cSThomas Abraham writel(val, &clk->gate_bus_cdrex);
64277b55e8cSThomas Abraham
64377b55e8cSThomas Abraham if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
64477b55e8cSThomas Abraham break;
64577b55e8cSThomas Abraham
64677b55e8cSThomas Abraham sdelay(10);
64777b55e8cSThomas Abraham }
64877b55e8cSThomas Abraham while (true) {
64977b55e8cSThomas Abraham writel(val & ~0x2, &clk->gate_bus_cdrex);
65077b55e8cSThomas Abraham lock1_info = readl(&phy1_ctrl->phy_con13);
65177b55e8cSThomas Abraham writel(val, &clk->gate_bus_cdrex);
65277b55e8cSThomas Abraham
65377b55e8cSThomas Abraham if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
65477b55e8cSThomas Abraham break;
65577b55e8cSThomas Abraham
65677b55e8cSThomas Abraham sdelay(10);
65777b55e8cSThomas Abraham }
65877b55e8cSThomas Abraham
65977b55e8cSThomas Abraham if (!reset) {
66077b55e8cSThomas Abraham /*
66177b55e8cSThomas Abraham * During Suspend-Resume & S/W-Reset, as soon as PMU releases
66277b55e8cSThomas Abraham * pad retention, CKE goes high. This causes memory contents
66377b55e8cSThomas Abraham * not to be retained during DRAM initialization. Therfore,
66477b55e8cSThomas Abraham * there is a new control register(0x100431e8[28]) which lets us
66577b55e8cSThomas Abraham * release pad retention and retain the memory content until the
66677b55e8cSThomas Abraham * initialization is complete.
66777b55e8cSThomas Abraham */
66877b55e8cSThomas Abraham writel(PAD_RETENTION_DRAM_COREBLK_VAL,
66977b55e8cSThomas Abraham &power->pad_retention_dram_coreblk_option);
67077b55e8cSThomas Abraham do {
67177b55e8cSThomas Abraham val = readl(&power->pad_retention_dram_status);
67277b55e8cSThomas Abraham } while (val != 0x1);
67377b55e8cSThomas Abraham
67477b55e8cSThomas Abraham /*
67577b55e8cSThomas Abraham * CKE PAD retention disables DRAM self-refresh mode.
67677b55e8cSThomas Abraham * Send auto refresh command for DRAM refresh.
67777b55e8cSThomas Abraham */
67877b55e8cSThomas Abraham for (i = 0; i < 128; i++) {
67977b55e8cSThomas Abraham for (chip = 0; chip < mem->chips_to_configure; chip++) {
68077b55e8cSThomas Abraham writel(DIRECT_CMD_REFA |
68177b55e8cSThomas Abraham (chip << DIRECT_CMD_CHIP_SHIFT),
68277b55e8cSThomas Abraham &drex0->directcmd);
68377b55e8cSThomas Abraham writel(DIRECT_CMD_REFA |
68477b55e8cSThomas Abraham (chip << DIRECT_CMD_CHIP_SHIFT),
68577b55e8cSThomas Abraham &drex1->directcmd);
68677b55e8cSThomas Abraham }
68777b55e8cSThomas Abraham }
68877b55e8cSThomas Abraham }
68977b55e8cSThomas Abraham
69077b55e8cSThomas Abraham if (mem->gate_leveling_enable) {
69177b55e8cSThomas Abraham writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
69277b55e8cSThomas Abraham writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
69377b55e8cSThomas Abraham
69477b55e8cSThomas Abraham setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
69577b55e8cSThomas Abraham setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
69677b55e8cSThomas Abraham
69777b55e8cSThomas Abraham val = PHY_CON2_RESET_VAL;
69877b55e8cSThomas Abraham val |= INIT_DESKEW_EN;
69977b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con2);
70077b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con2);
70177b55e8cSThomas Abraham
70277b55e8cSThomas Abraham val = readl(&phy0_ctrl->phy_con1);
70377b55e8cSThomas Abraham val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
70477b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con1);
70577b55e8cSThomas Abraham
70677b55e8cSThomas Abraham val = readl(&phy1_ctrl->phy_con1);
70777b55e8cSThomas Abraham val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
70877b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con1);
70977b55e8cSThomas Abraham
71077b55e8cSThomas Abraham n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
71177b55e8cSThomas Abraham n_lock_r = readl(&phy0_ctrl->phy_con12);
71277b55e8cSThomas Abraham n_lock_r &= ~CTRL_DLL_ON;
71377b55e8cSThomas Abraham n_lock_r |= n_lock_w_phy0;
71477b55e8cSThomas Abraham writel(n_lock_r, &phy0_ctrl->phy_con12);
71577b55e8cSThomas Abraham
71677b55e8cSThomas Abraham n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
71777b55e8cSThomas Abraham n_lock_r = readl(&phy1_ctrl->phy_con12);
71877b55e8cSThomas Abraham n_lock_r &= ~CTRL_DLL_ON;
71977b55e8cSThomas Abraham n_lock_r |= n_lock_w_phy1;
72077b55e8cSThomas Abraham writel(n_lock_r, &phy1_ctrl->phy_con12);
72177b55e8cSThomas Abraham
72277b55e8cSThomas Abraham val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
72377b55e8cSThomas Abraham for (chip = 0; chip < mem->chips_to_configure; chip++) {
72477b55e8cSThomas Abraham writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
72577b55e8cSThomas Abraham &drex0->directcmd);
72677b55e8cSThomas Abraham writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
72777b55e8cSThomas Abraham &drex1->directcmd);
72877b55e8cSThomas Abraham }
72977b55e8cSThomas Abraham
73077b55e8cSThomas Abraham setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
73177b55e8cSThomas Abraham setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
73277b55e8cSThomas Abraham
73377b55e8cSThomas Abraham setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
73477b55e8cSThomas Abraham setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
73577b55e8cSThomas Abraham
73677b55e8cSThomas Abraham val = readl(&phy0_ctrl->phy_con1);
73777b55e8cSThomas Abraham val &= ~(CTRL_GATEDURADJ_MASK);
73877b55e8cSThomas Abraham writel(val, &phy0_ctrl->phy_con1);
73977b55e8cSThomas Abraham
74077b55e8cSThomas Abraham val = readl(&phy1_ctrl->phy_con1);
74177b55e8cSThomas Abraham val &= ~(CTRL_GATEDURADJ_MASK);
74277b55e8cSThomas Abraham writel(val, &phy1_ctrl->phy_con1);
74377b55e8cSThomas Abraham
74477b55e8cSThomas Abraham writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
74577b55e8cSThomas Abraham i = TIMEOUT_US;
74677b55e8cSThomas Abraham while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
74777b55e8cSThomas Abraham RDLVL_COMPLETE_CHO) && (i > 0)) {
74877b55e8cSThomas Abraham /*
74977b55e8cSThomas Abraham * TODO(waihong): Comment on how long this take to
75077b55e8cSThomas Abraham * timeout
75177b55e8cSThomas Abraham */
75277b55e8cSThomas Abraham sdelay(100);
75377b55e8cSThomas Abraham i--;
75477b55e8cSThomas Abraham }
75577b55e8cSThomas Abraham if (!i)
75677b55e8cSThomas Abraham return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
75777b55e8cSThomas Abraham writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
75877b55e8cSThomas Abraham
75977b55e8cSThomas Abraham writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
76077b55e8cSThomas Abraham i = TIMEOUT_US;
76177b55e8cSThomas Abraham while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
76277b55e8cSThomas Abraham RDLVL_COMPLETE_CHO) && (i > 0)) {
76377b55e8cSThomas Abraham /*
76477b55e8cSThomas Abraham * TODO(waihong): Comment on how long this take to
76577b55e8cSThomas Abraham * timeout
76677b55e8cSThomas Abraham */
76777b55e8cSThomas Abraham sdelay(100);
76877b55e8cSThomas Abraham i--;
76977b55e8cSThomas Abraham }
77077b55e8cSThomas Abraham if (!i)
77177b55e8cSThomas Abraham return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
77277b55e8cSThomas Abraham writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
77377b55e8cSThomas Abraham
77477b55e8cSThomas Abraham writel(0, &phy0_ctrl->phy_con14);
77577b55e8cSThomas Abraham writel(0, &phy1_ctrl->phy_con14);
77677b55e8cSThomas Abraham
77777b55e8cSThomas Abraham val = (0x3 << DIRECT_CMD_BANK_SHIFT);
77877b55e8cSThomas Abraham for (chip = 0; chip < mem->chips_to_configure; chip++) {
77977b55e8cSThomas Abraham writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
78077b55e8cSThomas Abraham &drex0->directcmd);
78177b55e8cSThomas Abraham writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
78277b55e8cSThomas Abraham &drex1->directcmd);
78377b55e8cSThomas Abraham }
78477b55e8cSThomas Abraham
78577b55e8cSThomas Abraham /* Common Settings for Leveling */
78677b55e8cSThomas Abraham val = PHY_CON12_RESET_VAL;
78777b55e8cSThomas Abraham writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
78877b55e8cSThomas Abraham writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
78977b55e8cSThomas Abraham
79077b55e8cSThomas Abraham setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
79177b55e8cSThomas Abraham setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
79277b55e8cSThomas Abraham }
79377b55e8cSThomas Abraham
79477b55e8cSThomas Abraham /*
79577b55e8cSThomas Abraham * Do software read leveling
79677b55e8cSThomas Abraham *
79777b55e8cSThomas Abraham * Do this before we turn on auto refresh since the auto refresh can
79877b55e8cSThomas Abraham * be in conflict with the resync operation that's part of setting
79977b55e8cSThomas Abraham * read leveling.
80077b55e8cSThomas Abraham */
80177b55e8cSThomas Abraham if (!reset) {
80277b55e8cSThomas Abraham /* restore calibrated value after resume */
80377b55e8cSThomas Abraham dmc_set_read_offset_value(phy0_ctrl, readl(&pmu->pmu_spare1));
80477b55e8cSThomas Abraham dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2));
80577b55e8cSThomas Abraham } else {
80677b55e8cSThomas Abraham software_find_read_offset(phy0_ctrl, 0,
80777b55e8cSThomas Abraham CTRL_LOCK_COARSE(lock0_info));
80877b55e8cSThomas Abraham software_find_read_offset(phy1_ctrl, 1,
80977b55e8cSThomas Abraham CTRL_LOCK_COARSE(lock1_info));
81077b55e8cSThomas Abraham /* save calibrated value to restore after resume */
81177b55e8cSThomas Abraham writel(dmc_get_read_offset_value(phy0_ctrl), &pmu->pmu_spare1);
81277b55e8cSThomas Abraham writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2);
81377b55e8cSThomas Abraham }
81477b55e8cSThomas Abraham
81577b55e8cSThomas Abraham /* Send PALL command */
81677b55e8cSThomas Abraham dmc_config_prech(mem, &drex0->directcmd);
81777b55e8cSThomas Abraham dmc_config_prech(mem, &drex1->directcmd);
81877b55e8cSThomas Abraham
81977b55e8cSThomas Abraham writel(mem->memcontrol, &drex0->memcontrol);
82077b55e8cSThomas Abraham writel(mem->memcontrol, &drex1->memcontrol);
82177b55e8cSThomas Abraham
82277b55e8cSThomas Abraham /*
82377b55e8cSThomas Abraham * Set DMC Concontrol: Enable auto-refresh counter, provide
82477b55e8cSThomas Abraham * read data fetch cycles and enable DREX auto set powerdown
82577b55e8cSThomas Abraham * for input buffer of I/O in none read memory state.
82677b55e8cSThomas Abraham */
82777b55e8cSThomas Abraham writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
82877b55e8cSThomas Abraham (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
82977b55e8cSThomas Abraham DMC_CONCONTROL_IO_PD_CON(0x2),
83077b55e8cSThomas Abraham &drex0->concontrol);
83177b55e8cSThomas Abraham writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
83277b55e8cSThomas Abraham (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
83377b55e8cSThomas Abraham DMC_CONCONTROL_IO_PD_CON(0x2),
83477b55e8cSThomas Abraham &drex1->concontrol);
83577b55e8cSThomas Abraham
83677b55e8cSThomas Abraham /*
83777b55e8cSThomas Abraham * Enable Clock Gating Control for DMC
83877b55e8cSThomas Abraham * this saves around 25 mw dmc power as compared to the power
83977b55e8cSThomas Abraham * consumption without these bits enabled
84077b55e8cSThomas Abraham */
84177b55e8cSThomas Abraham setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
84277b55e8cSThomas Abraham setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
84377b55e8cSThomas Abraham
84477b55e8cSThomas Abraham /*
84577b55e8cSThomas Abraham * As per Exynos5800 UM ver 0.00 section 17.13.2.1
84677b55e8cSThomas Abraham * CONCONTROL register bit 3 [update_mode], Exynos5800 does not
84777b55e8cSThomas Abraham * support the PHY initiated update. And it is recommended to set
84877b55e8cSThomas Abraham * this field to 1'b1 during initialization
84977b55e8cSThomas Abraham *
85077b55e8cSThomas Abraham * When we apply PHY-initiated mode, DLL lock value is determined
85177b55e8cSThomas Abraham * once at DMC init time and not updated later when we change the MIF
85277b55e8cSThomas Abraham * voltage based on ASV group in kernel. Applying MC-initiated mode
85377b55e8cSThomas Abraham * makes sure that DLL tracing is ON so that silicon is able to
85477b55e8cSThomas Abraham * compensate the voltage variation.
85577b55e8cSThomas Abraham */
85677b55e8cSThomas Abraham val = readl(&drex0->concontrol);
85777b55e8cSThomas Abraham val |= CONCONTROL_UPDATE_MODE;
85877b55e8cSThomas Abraham writel(val, &drex0->concontrol);
85977b55e8cSThomas Abraham val = readl(&drex1->concontrol);
86077b55e8cSThomas Abraham val |= CONCONTROL_UPDATE_MODE;
86177b55e8cSThomas Abraham writel(val, &drex1->concontrol);
86277b55e8cSThomas Abraham
86377b55e8cSThomas Abraham return 0;
86477b55e8cSThomas Abraham }
86577b55e8cSThomas Abraham #endif
866