1*403e9cbcSPhilipp TomsichRK3368 dynamic memory controller driver 2*403e9cbcSPhilipp Tomsich======================================= 3*403e9cbcSPhilipp Tomsich 4*403e9cbcSPhilipp TomsichThe RK3368 DMC (dynamic memory controller) driver supports setup/initialisation 5*403e9cbcSPhilipp Tomsichduring TPL using configuration data from the DTS (i.e. OF_PLATDATA), based on 6*403e9cbcSPhilipp Tomsichthe following key configuration data: 7*403e9cbcSPhilipp Tomsich (a) a target-frequency (i.e. operating point) for the memory operation 8*403e9cbcSPhilipp Tomsich (b) a speed-bin (as defined in JESD-79) for the DDR3 used in hardware 9*403e9cbcSPhilipp Tomsich (c) a memory-schedule (i.e. mapping from physical addresses to the address 10*403e9cbcSPhilipp Tomsich pins of the memory bus) 11*403e9cbcSPhilipp Tomsich 12*403e9cbcSPhilipp TomsichRequired properties 13*403e9cbcSPhilipp Tomsich------------------- 14*403e9cbcSPhilipp Tomsich 15*403e9cbcSPhilipp Tomsich- compatible: "rockchip,rk3368-dmc" 16*403e9cbcSPhilipp Tomsich- reg 17*403e9cbcSPhilipp Tomsich protocol controller (PCTL) address and PHY controller (DDRPHY) address 18*403e9cbcSPhilipp Tomsich- rockchip,ddr-speed-bin 19*403e9cbcSPhilipp Tomsich the DDR3 device's speed-bin (as specified according to JESD-79) 20*403e9cbcSPhilipp Tomsich DDR3_800D (5-5-5) 21*403e9cbcSPhilipp Tomsich DDR3_800E (6-6-6) 22*403e9cbcSPhilipp Tomsich DDR3_1066E (6-6-6) 23*403e9cbcSPhilipp Tomsich DDR3_1066F (7-7-7) 24*403e9cbcSPhilipp Tomsich DDR3_1066G (8-8-8) 25*403e9cbcSPhilipp Tomsich DDR3_1333F (7-7-7) 26*403e9cbcSPhilipp Tomsich DDR3_1333G (8-8-8) 27*403e9cbcSPhilipp Tomsich DDR3_1333H (9-9-9) 28*403e9cbcSPhilipp Tomsich DDR3_1333J (10-10-10) 29*403e9cbcSPhilipp Tomsich DDR3_1600G (8-8-8) 30*403e9cbcSPhilipp Tomsich DDR3_1600H (9-9-9) 31*403e9cbcSPhilipp Tomsich DDR3_1600J (10-10-10) 32*403e9cbcSPhilipp Tomsich DDR3_1600K (11-11-11) 33*403e9cbcSPhilipp Tomsich DDR3_1866J (10-10-10) 34*403e9cbcSPhilipp Tomsich DDR3_1866K (11-11-11) 35*403e9cbcSPhilipp Tomsich DDR3_1866L (12-12-12) 36*403e9cbcSPhilipp Tomsich DDR3_1866M (13-13-13) 37*403e9cbcSPhilipp Tomsich DDR3_2133K (11-11-11) 38*403e9cbcSPhilipp Tomsich DDR3_2133L (12-12-12) 39*403e9cbcSPhilipp Tomsich DDR3_2133M (13-13-13) 40*403e9cbcSPhilipp Tomsich DDR3_2133N (14-14-14) 41*403e9cbcSPhilipp Tomsich- rockchip,ddr-frequency: 42*403e9cbcSPhilipp Tomsich target DDR clock frequency in Hz (not all frequencies may be supported, 43*403e9cbcSPhilipp Tomsich as there's some cooperation from the clock-driver required) 44*403e9cbcSPhilipp Tomsich- rockchip,memory-schedule: 45*403e9cbcSPhilipp Tomsich controls the decoding of physical addresses to DRAM addressing (i.e. how 46*403e9cbcSPhilipp Tomsich the physical address maps onto the address pins/chip-select of the device) 47*403e9cbcSPhilipp Tomsich DMC_MSCH_CBDR: column -> bank -> device -> row 48*403e9cbcSPhilipp Tomsich DMC_MSCH_CBRD: column -> band -> row -> device 49*403e9cbcSPhilipp Tomsich DMC_MSCH_CRBD: column -> row -> band -> device 50*403e9cbcSPhilipp Tomsich 51*403e9cbcSPhilipp TomsichExample (for DDR3-1600K and 800MHz) 52*403e9cbcSPhilipp Tomsich----------------------------------- 53*403e9cbcSPhilipp Tomsich 54*403e9cbcSPhilipp Tomsich #include <dt-bindings/memory/rk3368-dmc.h> 55*403e9cbcSPhilipp Tomsich 56*403e9cbcSPhilipp Tomsich dmc: dmc@ff610000 { 57*403e9cbcSPhilipp Tomsich u-boot,dm-pre-reloc; 58*403e9cbcSPhilipp Tomsich compatible = "rockchip,rk3368-dmc"; 59*403e9cbcSPhilipp Tomsich reg = <0 0xff610000 0 0x400 60*403e9cbcSPhilipp Tomsich 0 0xff620000 0 0x400>; 61*403e9cbcSPhilipp Tomsich }; 62*403e9cbcSPhilipp Tomsich 63*403e9cbcSPhilipp Tomsich &dmc { 64*403e9cbcSPhilipp Tomsich rockchip,ddr-speed-bin = <DDR3_1600K>; 65*403e9cbcSPhilipp Tomsich rockchip,ddr-frequency = <800000000>; 66*403e9cbcSPhilipp Tomsich rockchip,memory-schedule = <DMC_MSCH_CBRD>; 67*403e9cbcSPhilipp Tomsich }; 68