| /openbmc/linux/include/linux/ |
| H A D | clk.h | 55 struct clk *clk; member
72 struct clk *clk; member
89 struct clk *clk; member
150 int clk_get_phase(struct clk *clk);
234 struct clk *clk, in devm_clk_notifier_register() argument
290 int clk_prepare(struct clk *clk);
637 int clk_enable(struct clk *clk);
702 void clk_put(struct clk *clk);
847 int clk_set_parent(struct clk *clk, struct clk *parent);
856 struct clk *clk_get_parent(struct clk *clk);
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| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-imx5.c | 128 static struct clk *clk[IMX5_CLK_END]; variable
277 clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]); in mx5_clocks_common_init()
340 imx_check_clocks(clk, ARRAY_SIZE(clk)); in mx50_clocks_init()
347 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
348 clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]); in mx50_clocks_init()
431 imx_check_clocks(clk, ARRAY_SIZE(clk)); in mx51_clocks_init()
438 clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
441 clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]); in mx51_clocks_init()
585 imx_check_clocks(clk, ARRAY_SIZE(clk)); in mx53_clocks_init()
600 clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]); in mx53_clocks_init()
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| H A D | Makefile | 3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
9 mxc-clk-objs += clk-cpu.o
14 mxc-clk-objs += clk-gate2.o
17 mxc-clk-objs += clk-pfd.o
18 mxc-clk-objs += clk-pfdv2.o
19 mxc-clk-objs += clk-pllv1.o
20 mxc-clk-objs += clk-pllv2.o
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| H A D | clk-vf610.c | 113 static struct clk *clk[VF610_CLK_END]; variable
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
139 return clk; in vf610_get_fixed_clock()
236 clk_set_parent(clk[VF610_PLL1_BYPASS], clk[VF610_CLK_PLL1]); in vf610_clocks_init()
237 clk_set_parent(clk[VF610_PLL2_BYPASS], clk[VF610_CLK_PLL2]); in vf610_clocks_init()
238 clk_set_parent(clk[VF610_PLL3_BYPASS], clk[VF610_CLK_PLL3]); in vf610_clocks_init()
239 clk_set_parent(clk[VF610_PLL4_BYPASS], clk[VF610_CLK_PLL4]); in vf610_clocks_init()
240 clk_set_parent(clk[VF610_PLL5_BYPASS], clk[VF610_CLK_PLL5]); in vf610_clocks_init()
241 clk_set_parent(clk[VF610_PLL6_BYPASS], clk[VF610_CLK_PLL6]); in vf610_clocks_init()
242 clk_set_parent(clk[VF610_PLL7_BYPASS], clk[VF610_CLK_PLL7]); in vf610_clocks_init()
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| H A D | clk-imx27.c | 48 static struct clk *clk[IMX27_CLK_MAX]; variable
55 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
58 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
70 clk[IMX27_CLK_IPG] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx27_clocks_init()
161 imx_check_clocks(clk, ARRAY_SIZE(clk)); in _mx27_clocks_init()
163 clk_register_clkdev(clk[IMX27_CLK_CPU_DIV], NULL, "cpu0"); in _mx27_clocks_init()
165 clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]); in _mx27_clocks_init()
191 clk_data.clks = clk; in mx27_clocks_init_dt()
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| H A D | clk-imx25.c | 75 static struct clk *clk[clk_max]; variable
81 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
108 clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR), 30); in __mx25_clocks_init()
209 imx_check_clocks(clk, ARRAY_SIZE(clk)); in __mx25_clocks_init()
211 clk_prepare_enable(clk[emi_ahb]); in __mx25_clocks_init()
214 clk_set_parent(clk[per5_sel], clk[ahb]); in __mx25_clocks_init()
220 clk_set_parent(clk[cko_sel], clk[ipg]); in __mx25_clocks_init()
234 clk_data.clks = clk; in mx25_clocks_init_dt()
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| H A D | clk-imx35.c | 82 static struct clk *clk[clk_max]; variable
218 imx_check_clocks(clk, ARRAY_SIZE(clk)); in _mx35_clocks_init()
220 clk_prepare_enable(clk[spba_gate]); in _mx35_clocks_init()
221 clk_prepare_enable(clk[gpio1_gate]); in _mx35_clocks_init()
222 clk_prepare_enable(clk[gpio2_gate]); in _mx35_clocks_init()
224 clk_prepare_enable(clk[iim_gate]); in _mx35_clocks_init()
225 clk_prepare_enable(clk[emi_gate]); in _mx35_clocks_init()
226 clk_prepare_enable(clk[max_gate]); in _mx35_clocks_init()
235 clk_prepare_enable(clk[scc_gate]); in _mx35_clocks_init()
246 clk_data.clks = clk; in mx35_clocks_init_dt()
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| /openbmc/linux/drivers/sh/clk/ |
| H A D | cpg.c | 19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
39 static int sh_clk_mstp_enable(struct clk *clk) in sh_clk_mstp_enable() argument
41 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
61 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
70 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
201 if (!clk->parent_table || !clk->parent_num) in sh_clk_init_parent()
217 clk_reparent(clk, clk->parent_table[val]); in sh_clk_init_parent()
279 static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent) in sh_clk_div6_set_parent() argument
336 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent) in sh_clk_div4_set_parent() argument
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| H A D | core.c | 246 clk->ops->disable(clk); in __clk_disable()
330 static struct clk *lookup_root_clock(struct clk *clk) in lookup_root_clock() argument
333 clk = clk->parent; in lookup_root_clock()
442 clk->ops->init(clk); in clk_register()
500 clk->rate = clk->ops->recalc(clk); in clk_set_rate()
530 clk->rate = clk->ops->recalc(clk); in clk_set_parent()
532 clk, clk->parent, clk->rate); in clk_set_parent()
543 struct clk *clk_get_parent(struct clk *clk) in clk_get_parent() argument
607 struct clk *clk; in clk_late_init() local
614 if (!clk->usecount && clk->ops && clk->ops->disable) in clk_late_init()
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| /openbmc/linux/arch/mips/lantiq/ |
| H A D | clk.c | 63 return clk && !IS_ERR(clk); in clk_good()
85 if (clk->rates && *clk->rates) { in clk_set_rate()
105 if (clk->rates && *clk->rates) { in clk_round_rate()
118 int clk_enable(struct clk *clk) in clk_enable() argument
124 return clk->enable(clk); in clk_enable()
136 clk->disable(clk); in clk_disable()
146 return clk->activate(clk); in clk_activate()
158 clk->deactivate(clk); in clk_deactivate()
162 struct clk *clk_get_parent(struct clk *clk) in clk_get_parent() argument
168 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
22 clk-mt6795-pericfg.o clk-mt6795-topckgen.o
41 obj-$(CONFIG_COMMON_CLK_MT2712) += clk-mt2712-apmixedsys.o clk-mt2712.o
49 obj-$(CONFIG_COMMON_CLK_MT7622) += clk-mt7622-apmixedsys.o clk-mt7622.o \
65 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o
66 obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o
73 clk-mt8173-pericfg.o clk-mt8173-topckgen.o
78 obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183-apmixedsys.o clk-mt8183.o
104 clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o
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| /openbmc/linux/arch/m68k/coldfire/ |
| H A D | clk.c | 31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
76 int clk_enable(struct clk *clk) in clk_enable() argument
85 clk->clk_ops->enable(clk); in clk_enable()
92 void clk_disable(struct clk *clk) in clk_disable() argument
101 clk->clk_ops->disable(clk); in clk_disable()
130 int clk_set_parent(struct clk *clk, struct clk *parent) in clk_set_parent() argument
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| /openbmc/linux/drivers/clk/spear/ |
| H A D | spear3xx_clock.c | 141 struct clk *clk; in spear300_clk_init() local
171 struct clk *clk; in spear310_clk_init() local
175 clk_register_clkdev(clk, "emi", NULL); in spear310_clk_init()
183 clk_register_clkdev(clk, NULL, "tdm"); in spear310_clk_init()
247 struct clk *ras_apb_clk) in spear320_clk_init()
249 struct clk *clk; in spear320_clk_init() local
261 clk_register_clkdev(clk, "emi", NULL); in spear320_clk_init()
345 clk_set_parent(clk, ras_apb_clk); in spear320_clk_init()
354 clk_set_parent(clk, ras_apb_clk); in spear320_clk_init()
390 struct clk *clk, *clk1, *ras_apb_clk; in spear3xx_clk_init() local
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| H A D | spear1310_clock.c | 384 struct clk *clk, *clk1; in spear1310_clk_init() local
485 clk_register_clkdev(clk, "ddr_clk", NULL); in spear1310_clk_init()
490 clk_register_clkdev(clk, "cpu_clk", NULL); in spear1310_clk_init()
498 clk_register_clkdev(clk, NULL, "smp_twd"); in spear1310_clk_init()
502 clk_register_clkdev(clk, "ahb_clk", NULL); in spear1310_clk_init()
517 clk_register_clkdev(clk, NULL, "gpt0"); in spear1310_clk_init()
527 clk_register_clkdev(clk, NULL, "gpt1"); in spear1310_clk_init()
537 clk_register_clkdev(clk, NULL, "gpt2"); in spear1310_clk_init()
547 clk_register_clkdev(clk, NULL, "gpt3"); in spear1310_clk_init()
607 clk_register_clkdev(clk, NULL, "c3"); in spear1310_clk_init()
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| H A D | spear6xx_clock.c | 116 struct clk *clk, *clk1; in spear6xx_clk_init() local
132 clk_register_clkdev(clk, "pll3_clk", NULL); in spear6xx_clk_init()
137 clk_register_clkdev(clk, "vco1_clk", NULL); in spear6xx_clk_init()
153 clk_register_clkdev(clk, "cpu_clk", NULL); in spear6xx_clk_init()
158 clk_register_clkdev(clk, "ahb_clk", NULL); in spear6xx_clk_init()
194 clk_register_clkdev(clk, NULL, "firda"); in spear6xx_clk_init()
220 clk_register_clkdev(clk, NULL, "gpt0"); in spear6xx_clk_init()
229 clk_register_clkdev(clk, NULL, "gpt1"); in spear6xx_clk_init()
242 clk_register_clkdev(clk, NULL, "gpt2"); in spear6xx_clk_init()
255 clk_register_clkdev(clk, NULL, "gpt3"); in spear6xx_clk_init()
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| H A D | spear1340_clock.c | 441 struct clk *clk, *clk1; in spear1340_clk_init() local
542 clk_register_clkdev(clk, "ddr_clk", NULL); in spear1340_clk_init()
563 clk_register_clkdev(clk, "cpu_clk", NULL); in spear1340_clk_init()
575 clk_register_clkdev(clk, NULL, "smp_twd"); in spear1340_clk_init()
581 clk_register_clkdev(clk, "ahb_clk", NULL); in spear1340_clk_init()
585 clk_register_clkdev(clk, "apb_clk", NULL); in spear1340_clk_init()
596 clk_register_clkdev(clk, NULL, "gpt0"); in spear1340_clk_init()
606 clk_register_clkdev(clk, NULL, "gpt1"); in spear1340_clk_init()
616 clk_register_clkdev(clk, NULL, "gpt2"); in spear1340_clk_init()
626 clk_register_clkdev(clk, NULL, "gpt3"); in spear1340_clk_init()
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| /openbmc/qemu/hw/core/ |
| H A D | clock.c | 24 clk->canonical_path = object_get_canonical_path(OBJECT(clk)); in clock_setup_canonical_path()
30 Clock *clk; in clock_new() local
36 clk = CLOCK(obj); in clock_new()
39 return clk; in clock_new()
45 clk->callback = cb; in clock_set_callback()
60 trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), in clock_set()
73 return muldiv64(clk->period, clk->multiplier, clk->divider); in clock_get_child_period()
82 if (clk->callback && (clk->callback_events & event)) { in clock_call_callback()
83 clk->callback(clk->callback_opaque, event); in clock_call_callback()
150 trace_clock_set_mul_div(CLOCK_PATH(clk), clk->multiplier, multiplier, in clock_set_mul_div()
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| /openbmc/linux/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 32 struct clk **clk_data = data; in ux500_twocell_get()
130 struct clk *clk, *rtc_clk, *twd_clk; in u8500_clk_init() local
305 PRCC_PCLK_STORE(clk, 1, 0); in u8500_clk_init()
309 PRCC_PCLK_STORE(clk, 1, 1); in u8500_clk_init()
313 PRCC_PCLK_STORE(clk, 1, 2); in u8500_clk_init()
317 PRCC_PCLK_STORE(clk, 1, 3); in u8500_clk_init()
321 PRCC_PCLK_STORE(clk, 1, 4); in u8500_clk_init()
325 PRCC_PCLK_STORE(clk, 1, 5); in u8500_clk_init()
329 PRCC_PCLK_STORE(clk, 1, 6); in u8500_clk_init()
333 PRCC_PCLK_STORE(clk, 1, 7); in u8500_clk_init()
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| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos5.c | 549 struct exynos5_clock *clk = in exynos5250_system_clock_init() local
607 writel(val, &clk->div_cpu0); in exynos5250_system_clock_init()
732 val = readl(&clk->src_cpu); in exynos5250_system_clock_init()
734 writel(val, &clk->src_cpu); in exynos5250_system_clock_init()
808 writel(0, &clk->src_top6); in exynos5420_system_clock_init()
810 writel(0, &clk->src_cdrex); in exynos5420_system_clock_init()
923 writel(0, &clk->src_top10); in exynos5420_system_clock_init()
924 writel(0, &clk->src_top11); in exynos5420_system_clock_init()
925 writel(0, &clk->src_top12); in exynos5420_system_clock_init()
979 struct exynos5_clock *clk = in clock_init_dp_clock() local
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| H A D | clock_init_exynos4.c | 41 struct exynos4_clock *clk = in system_clock_init() local
44 writel(CLK_SRC_CPU_VAL, &clk->src_cpu); in system_clock_init()
50 writel(CLK_SRC_DMC_VAL, &clk->src_dmc); in system_clock_init()
55 writel(CLK_SRC_CAM_VAL, &clk->src_cam); in system_clock_init()
56 writel(CLK_SRC_MFC_VAL, &clk->src_mfc); in system_clock_init()
57 writel(CLK_SRC_G3D_VAL, &clk->src_g3d); in system_clock_init()
68 writel(CLK_DIV_TOP_VAL, &clk->div_top); in system_clock_init()
79 writel(PLL_LOCKTIME, &clk->apll_lock); in system_clock_init()
80 writel(PLL_LOCKTIME, &clk->mpll_lock); in system_clock_init()
81 writel(PLL_LOCKTIME, &clk->epll_lock); in system_clock_init()
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| /openbmc/u-boot/drivers/clk/tegra/ |
| H A D | tegra-car-clk.c | 12 static int tegra_car_clk_request(struct clk *clk) in tegra_car_clk_request() argument
14 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_request()
15 clk->id); in tegra_car_clk_request()
31 static int tegra_car_clk_free(struct clk *clk) in tegra_car_clk_free() argument
33 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev, in tegra_car_clk_free()
34 clk->id); in tegra_car_clk_free()
39 static ulong tegra_car_clk_get_rate(struct clk *clk) in tegra_car_clk_get_rate() argument
44 clk->id); in tegra_car_clk_get_rate()
55 clk->dev, clk->id); in tegra_car_clk_set_rate()
61 static int tegra_car_clk_enable(struct clk *clk) in tegra_car_clk_enable() argument
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| /openbmc/qemu/hw/misc/ |
| H A D | omap_clk.c | 27 struct clk { struct
30 struct clk *parent; argument
31 struct clk *child1; argument
1099 void omap_clk_adduser(struct clk *clk, qemu_irq user) in omap_clk_adduser() argument
1117 void omap_clk_get(struct clk *clk) in omap_clk_get() argument
1122 void omap_clk_put(struct clk *clk) in omap_clk_put() argument
1128 static void omap_clk_update(struct clk *clk) in omap_clk_update() argument
1165 static void omap_clk_rate_update(struct clk *clk) in omap_clk_rate_update() argument
1178 void omap_clk_reparent(struct clk *clk, struct clk *parent) in omap_clk_reparent() argument
1197 void omap_clk_onoff(struct clk *clk, int on) in omap_clk_onoff() argument
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | stih410-clock.dtsi | 20 clk_sysin: clk-sysin {
173 "clk-fdma",
174 "clk-nand",
175 "clk-hva",
182 "clk-mmc-0",
183 "clk-mmc-1",
247 "clk-pcm-1",
248 "clk-pcm-2",
297 "clk-denc",
302 "clk-dvo",
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| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | base.c | 195 ret = clk->func->calc(clk, cstate); in nvkm_cstate_prog()
197 ret = clk->func->prog(clk); in nvkm_cstate_prog()
198 clk->func->tidy(clk); in nvkm_cstate_prog()
311 clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc, in nvkm_pstate_work()
312 clk->astate, clk->temp, clk->dstate); in nvkm_pstate_work()
314 pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc; in nvkm_pstate_work()
537 clk->astate = min(clk->astate, clk->state_nr - 1); in nvkm_clk_astate()
556 clk->dstate = min(clk->dstate, clk->state_nr - 1); in nvkm_clk_dstate()
585 clk->func->fini(clk); in nvkm_clk_fini()
613 return clk->func->init(clk); in nvkm_clk_init()
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| /openbmc/linux/kernel/time/ |
| H A D | posix-clock.c | 45 if (!clk) in posix_clock_read()
61 if (!clk) in posix_clock_poll()
65 result = clk->ops.poll(clk, fp, wait); in posix_clock_poll()
78 if (!clk) in posix_clock_ioctl()
82 err = clk->ops.ioctl(clk, cmd, arg); in posix_clock_ioctl()
100 err = clk->ops.ioctl(clk, cmd, arg); in posix_clock_compat_ioctl()
121 err = clk->ops.open(clk, fp->f_mode); in posix_clock_open()
140 err = clk->ops.release(clk); in posix_clock_release()
175 clk->cdev.owner = clk->ops.owner; in posix_clock_register()
184 cdev_device_del(&clk->cdev, clk->dev); in posix_clock_unregister()
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