| /openbmc/linux/include/linux/ |
| H A D | clk.h | 17 struct clk;
55 struct clk *clk; member
72 struct clk *clk; member
89 struct clk *clk; member
103 int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
110 int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
120 int devm_clk_notifier_register(struct device *dev, struct clk *clk,
131 long clk_get_accuracy(struct clk *clk);
141 int clk_set_phase(struct clk *clk, int degrees);
150 int clk_get_phase(struct clk *clk);
[all …]
|
| /openbmc/linux/drivers/clk/imx/ |
| H A D | clk-imx5.c | 128 static struct clk *clk[IMX5_CLK_END]; variable
133 clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in mx5_clocks_common_init()
134 clk[IMX5_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in mx5_clocks_common_init()
135 clk[IMX5_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in mx5_clocks_common_init()
136 clk[IMX5_CLK_CKIH1] = imx_obtain_fixed_clock("ckih1", 0); in mx5_clocks_common_init()
137 clk[IMX5_CLK_CKIH2] = imx_obtain_fixed_clock("ckih2", 0); in mx5_clocks_common_init()
139 clk[IMX5_CLK_PER_LP_APM] = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1, in mx5_clocks_common_init()
141 clk[IMX5_CLK_PER_PRED1] = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2); in mx5_clocks_common_init()
142 clk[IMX5_CLK_PER_PRED2] = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3); in mx5_clocks_common_init()
143 clk[IMX5_CLK_PER_PODF] = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3); in mx5_clocks_common_init()
[all …]
|
| H A D | clk-vf610.c | 113 static struct clk *clk[VF610_CLK_END]; variable
131 static struct clk * __init vf610_get_fixed_clock( in vf610_get_fixed_clock()
134 struct clk *clk = of_clk_get_by_name(ccm_node, name); in vf610_get_fixed_clock() local
137 if (IS_ERR(clk)) in vf610_get_fixed_clock()
138 clk = imx_obtain_fixed_clock(name, 0); in vf610_get_fixed_clock()
139 return clk; in vf610_get_fixed_clock()
184 clk[VF610_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in vf610_clocks_init()
185 clk[VF610_CLK_SIRC_128K] = imx_clk_fixed("sirc_128k", 128000); in vf610_clocks_init()
186 clk[VF610_CLK_SIRC_32K] = imx_clk_fixed("sirc_32k", 32000); in vf610_clocks_init()
187 clk[VF610_CLK_FIRC] = imx_clk_fixed("firc", 24000000); in vf610_clocks_init()
[all …]
|
| H A D | Makefile | 3 mxc-clk-objs += clk.o
4 mxc-clk-objs += clk-busy.o
5 mxc-clk-objs += clk-composite-7ulp.o
6 mxc-clk-objs += clk-composite-8m.o
7 mxc-clk-objs += clk-composite-93.o
8 mxc-clk-objs += clk-fracn-gppll.o
9 mxc-clk-objs += clk-cpu.o
10 mxc-clk-objs += clk-divider-gate.o
11 mxc-clk-objs += clk-fixup-div.o
12 mxc-clk-objs += clk-fixup-mux.o
[all …]
|
| H A D | clk-imx27.c | 48 static struct clk *clk[IMX27_CLK_MAX]; variable
55 clk[IMX27_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in _mx27_clocks_init()
56 clk[IMX27_CLK_CKIH] = imx_clk_fixed("ckih", fref); in _mx27_clocks_init()
57 clk[IMX27_CLK_CKIL] = imx_clk_fixed("ckil", 32768); in _mx27_clocks_init()
58 clk[IMX27_CLK_FPM] = imx_clk_fixed_factor("fpm", "ckil", 1024, 1); in _mx27_clocks_init()
59 clk[IMX27_CLK_CKIH_DIV1P5] = imx_clk_fixed_factor("ckih_div1p5", "ckih_gate", 2, 3); in _mx27_clocks_init()
60 clk[IMX27_CLK_CKIH_GATE] = imx_clk_gate_dis("ckih_gate", "ckih", CCM_CSCR, 3); in _mx27_clocks_init()
61 …clk[IMX27_CLK_MPLL_OSC_SEL] = imx_clk_mux("mpll_osc_sel", CCM_CSCR, 4, 1, mpll_osc_sel_clks, ARRAY… in _mx27_clocks_init()
62 …clk[IMX27_CLK_MPLL_SEL] = imx_clk_mux("mpll_sel", CCM_CSCR, 16, 1, mpll_sel_clks, ARRAY_SIZE(mpll_… in _mx27_clocks_init()
63 clk[IMX27_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX27, "mpll", "mpll_sel", CCM_MPCTL0); in _mx27_clocks_init()
[all …]
|
| H A D | clk-imx25.c | 75 static struct clk *clk[clk_max]; variable
81 clk[dummy] = imx_clk_fixed("dummy", 0); in __mx25_clocks_init()
82 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "mpll", "osc", ccm(CCM_MPCTL)); in __mx25_clocks_init()
83 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX25, "upll", "osc", ccm(CCM_UPCTL)); in __mx25_clocks_init()
84 clk[mpll_cpu_3_4] = imx_clk_fixed_factor("mpll_cpu_3_4", "mpll", 3, 4); in __mx25_clocks_init()
85 …clk[cpu_sel] = imx_clk_mux("cpu_sel", ccm(CCM_CCTL), 14, 1, cpu_sel_clks, ARRAY_SIZE(cpu_sel_clks)… in __mx25_clocks_init()
86 clk[cpu] = imx_clk_divider("cpu", "cpu_sel", ccm(CCM_CCTL), 30, 2); in __mx25_clocks_init()
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
88 clk[usb_div] = imx_clk_divider("usb_div", "upll", ccm(CCM_CCTL), 16, 6); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
[all …]
|
| H A D | clk-imx35.c | 82 static struct clk *clk[clk_max]; variable
106 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
107 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
114 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); in _mx35_clocks_init()
116 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in _mx35_clocks_init()
118 if (clk_get_rate(clk[arm]) > 400000000) in _mx35_clocks_init()
129 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); in _mx35_clocks_init()
[all …]
|
| H A D | clk-imx31.c | 50 static struct clk *clk[clk_max]; variable
55 clk[dummy] = imx_clk_fixed("dummy", 0); in _mx31_clocks_init()
56 clk[ckih] = imx_clk_fixed("ckih", fref); in _mx31_clocks_init()
57 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx31_clocks_init()
58 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL); in _mx31_clocks_init()
59 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL); in _mx31_clocks_init()
60 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL); in _mx31_clocks_init()
61 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_… in _mx31_clocks_init()
62 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); in _mx31_clocks_init()
63 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
[all …]
|
| /openbmc/linux/drivers/sh/clk/ |
| H A D | cpg.c | 19 static unsigned int sh_clk_read(struct clk *clk) in sh_clk_read() argument
21 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_read()
22 return ioread8(clk->mapped_reg); in sh_clk_read()
23 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_read()
24 return ioread16(clk->mapped_reg); in sh_clk_read()
26 return ioread32(clk->mapped_reg); in sh_clk_read()
29 static void sh_clk_write(int value, struct clk *clk) in sh_clk_write() argument
31 if (clk->flags & CLK_ENABLE_REG_8BIT) in sh_clk_write()
32 iowrite8(value, clk->mapped_reg); in sh_clk_write()
33 else if (clk->flags & CLK_ENABLE_REG_16BIT) in sh_clk_write()
[all …]
|
| H A D | core.c | 39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
137 long clk_rate_table_round(struct clk *clk, in clk_rate_table_round() argument
143 .max = clk->nr_freqs - 1, in clk_rate_table_round()
149 if (clk->nr_freqs < 1) in clk_rate_table_round()
161 long clk_rate_div_range_round(struct clk *clk, unsigned int div_min, in clk_rate_div_range_round() argument
168 .arg = clk_get_parent(clk), in clk_rate_div_range_round()
181 long clk_rate_mult_range_round(struct clk *clk, unsigned int mult_min, in clk_rate_mult_range_round() argument
188 .arg = clk_get_parent(clk), in clk_rate_mult_range_round()
[all …]
|
| /openbmc/linux/arch/mips/lantiq/ |
| H A D | clk.c | 27 static struct clk cpu_clk_generic[4];
38 struct clk *clk_get_cpu(void) in clk_get_cpu()
43 struct clk *clk_get_fpi(void) in clk_get_fpi()
49 struct clk *clk_get_io(void) in clk_get_io()
55 struct clk *clk_get_ppe(void) in clk_get_ppe()
61 static inline int clk_good(struct clk *clk) in clk_good() argument
63 return clk && !IS_ERR(clk); in clk_good()
66 unsigned long clk_get_rate(struct clk *clk) in clk_get_rate() argument
68 if (unlikely(!clk_good(clk))) in clk_get_rate()
71 if (clk->rate != 0) in clk_get_rate()
[all …]
|
| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | Makefile | 2 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o clk-cpumux.o rese…
3 obj-$(CONFIG_COMMON_CLK_MEDIATEK_FHCTL) += clk-fhctl.o clk-pllfh.o
5 obj-$(CONFIG_COMMON_CLK_MT6765) += clk-mt6765.o
6 obj-$(CONFIG_COMMON_CLK_MT6765_AUDIOSYS) += clk-mt6765-audio.o
7 obj-$(CONFIG_COMMON_CLK_MT6765_CAMSYS) += clk-mt6765-cam.o
8 obj-$(CONFIG_COMMON_CLK_MT6765_IMGSYS) += clk-mt6765-img.o
9 obj-$(CONFIG_COMMON_CLK_MT6765_MIPI0ASYS) += clk-mt6765-mipi0a.o
10 obj-$(CONFIG_COMMON_CLK_MT6765_MMSYS) += clk-mt6765-mm.o
11 obj-$(CONFIG_COMMON_CLK_MT6765_VCODECSYS) += clk-mt6765-vcodec.o
12 obj-$(CONFIG_COMMON_CLK_MT6779) += clk-mt6779.o
[all …]
|
| /openbmc/linux/drivers/clk/spear/ |
| H A D | spear3xx_clock.c | 141 struct clk *clk; in spear300_clk_init() local
143 clk = clk_register_fixed_factor(NULL, "clcd_clk", "ras_pll3_clk", 0, in spear300_clk_init()
145 clk_register_clkdev(clk, NULL, "60000000.clcd"); in spear300_clk_init()
147 clk = clk_register_fixed_factor(NULL, "fsmc_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
149 clk_register_clkdev(clk, NULL, "94000000.flash"); in spear300_clk_init()
151 clk = clk_register_fixed_factor(NULL, "sdhci_clk", "ras_ahb_clk", 0, 1, in spear300_clk_init()
153 clk_register_clkdev(clk, NULL, "70000000.sdhci"); in spear300_clk_init()
155 clk = clk_register_fixed_factor(NULL, "gpio1_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
157 clk_register_clkdev(clk, NULL, "a9000000.gpio"); in spear300_clk_init()
159 clk = clk_register_fixed_factor(NULL, "kbd_clk", "ras_apb_clk", 0, 1, in spear300_clk_init()
[all …]
|
| H A D | spear1310_clock.c | 384 struct clk *clk, *clk1; in spear1310_clk_init() local
386 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1310_clk_init()
387 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1310_clk_init()
389 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1310_clk_init()
390 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1310_clk_init()
392 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1310_clk_init()
393 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1310_clk_init()
395 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1310_clk_init()
396 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1310_clk_init()
398 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1310_clk_init()
[all …]
|
| H A D | spear1340_clock.c | 441 struct clk *clk, *clk1; in spear1340_clk_init() local
443 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear1340_clk_init()
444 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear1340_clk_init()
446 clk = clk_register_fixed_rate(NULL, "osc_24m_clk", NULL, 0, 24000000); in spear1340_clk_init()
447 clk_register_clkdev(clk, "osc_24m_clk", NULL); in spear1340_clk_init()
449 clk = clk_register_fixed_rate(NULL, "osc_25m_clk", NULL, 0, 25000000); in spear1340_clk_init()
450 clk_register_clkdev(clk, "osc_25m_clk", NULL); in spear1340_clk_init()
452 clk = clk_register_fixed_rate(NULL, "gmii_pad_clk", NULL, 0, 125000000); in spear1340_clk_init()
453 clk_register_clkdev(clk, "gmii_pad_clk", NULL); in spear1340_clk_init()
455 clk = clk_register_fixed_rate(NULL, "i2s_src_pad_clk", NULL, 0, in spear1340_clk_init()
[all …]
|
| H A D | spear6xx_clock.c | 116 struct clk *clk, *clk1; in spear6xx_clk_init() local
118 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000); in spear6xx_clk_init()
119 clk_register_clkdev(clk, "osc_32k_clk", NULL); in spear6xx_clk_init()
121 clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000); in spear6xx_clk_init()
122 clk_register_clkdev(clk, "osc_30m_clk", NULL); in spear6xx_clk_init()
125 clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0, in spear6xx_clk_init()
127 clk_register_clkdev(clk, NULL, "rtc-spear"); in spear6xx_clk_init()
130 clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0, in spear6xx_clk_init()
132 clk_register_clkdev(clk, "pll3_clk", NULL); in spear6xx_clk_init()
134 clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk", in spear6xx_clk_init()
[all …]
|
| /openbmc/linux/arch/m68k/coldfire/ |
| H A D | clk.c | 31 void __clk_init_enabled(struct clk *clk) in __clk_init_enabled() argument
33 clk->enabled = 1; in __clk_init_enabled()
34 clk->clk_ops->enable(clk); in __clk_init_enabled()
37 void __clk_init_disabled(struct clk *clk) in __clk_init_disabled() argument
39 clk->enabled = 0; in __clk_init_disabled()
40 clk->clk_ops->disable(clk); in __clk_init_disabled()
43 static void __clk_enable0(struct clk *clk) in __clk_enable0() argument
45 __raw_writeb(clk->slot, MCFPM_PPMCR0); in __clk_enable0()
48 static void __clk_disable0(struct clk *clk) in __clk_disable0() argument
50 __raw_writeb(clk->slot, MCFPM_PPMSR0); in __clk_disable0()
[all …]
|
| /openbmc/linux/drivers/clk/ux500/ |
| H A D | u8500_of_clk.c | 18 static struct clk *prcc_pclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
19 static struct clk *prcc_kclk[(PRCC_NUM_PERIPH_CLUSTERS + 1) * PRCC_PERIPHS_PER_CLUSTER];
22 #define PRCC_SHOW(clk, base, bit) \ argument
23 clk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit]
24 #define PRCC_PCLK_STORE(clk, base, bit) \ argument
25 prcc_pclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
26 #define PRCC_KCLK_STORE(clk, base, bit) \ argument
27 prcc_kclk[(base * PRCC_PERIPHS_PER_CLUSTER) + bit] = clk
29 static struct clk *ux500_twocell_get(struct of_phandle_args *clkspec, in ux500_twocell_get()
32 struct clk **clk_data = data; in ux500_twocell_get()
[all …]
|
| /openbmc/qemu/hw/core/ |
| H A D | clock.c | 23 void clock_setup_canonical_path(Clock *clk) in clock_setup_canonical_path() argument
25 g_free(clk->canonical_path); in clock_setup_canonical_path()
26 clk->canonical_path = object_get_canonical_path(OBJECT(clk)); in clock_setup_canonical_path()
32 Clock *clk; in clock_new() local
38 clk = CLOCK(obj); in clock_new()
39 clock_setup_canonical_path(clk); in clock_new()
41 return clk; in clock_new()
44 void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque, in clock_set_callback() argument
47 clk->callback = cb; in clock_set_callback()
48 clk->callback_opaque = opaque; in clock_set_callback()
[all …]
|
| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock_init_exynos5.c | 549 struct exynos5_clock *clk = in exynos5250_system_clock_init() local
558 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK); in exynos5250_system_clock_init()
560 val = readl(&clk->mux_stat_cpu); in exynos5250_system_clock_init()
563 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK); in exynos5250_system_clock_init()
565 val = readl(&clk->mux_stat_core1); in exynos5250_system_clock_init()
568 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); in exynos5250_system_clock_init()
569 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); in exynos5250_system_clock_init()
570 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); in exynos5250_system_clock_init()
571 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); in exynos5250_system_clock_init()
575 val = readl(&clk->mux_stat_top2); in exynos5250_system_clock_init()
[all …]
|
| /openbmc/qemu/hw/misc/ |
| H A D | omap_clk.c | 27 struct clk { struct
30 struct clk *parent; argument
31 struct clk *child1; argument
32 struct clk *sibling; argument
50 static struct clk xtal_osc12m = { argument
56 static struct clk xtal_osc32k = {
62 static struct clk ck_ref = {
71 static struct clk dpll1 = {
78 static struct clk dpll2 = {
84 static struct clk dpll3 = {
[all …]
|
| /openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| H A D | base.c | 41 nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust, in nvkm_clk_adjust() argument
44 struct nvkm_bios *bios = clk->subdev.device->bios; in nvkm_clk_adjust()
79 nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate, in nvkm_cstate_valid() argument
82 const struct nvkm_domain *domain = clk->domains; in nvkm_cstate_valid()
83 struct nvkm_volt *volt = clk->subdev.device->volt; in nvkm_cstate_valid()
89 switch (clk->boost_mode) { in nvkm_cstate_valid()
91 if (clk->base_khz && freq > clk->base_khz) in nvkm_cstate_valid()
95 if (clk->boost_khz && freq > clk->boost_khz) in nvkm_cstate_valid()
112 nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate, in nvkm_cstate_find_best() argument
115 struct nvkm_device *device = clk->subdev.device; in nvkm_cstate_find_best()
[all …]
|
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | stih410-clock.dtsi | 15 compatible = "st,stih410-clk", "simple-bus";
20 clk_sysin: clk-sysin {
30 arm_periph_clk: clk-m-a9-periphs {
58 clk_m_a9: clk-m-a9@92b0000 {
72 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
78 clock-output-names = "clk-m-a9-ext2f-div2";
92 clock-output-names = "clk-s-icn-reg-0";
99 clk_s_a0_pll: clk-s-a0-pll {
105 clock-output-names = "clk-s-a0-pll-ofd-0";
106 clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
[all …]
|
| /openbmc/linux/arch/arm/mach-omap1/ |
| H A D | clock.c | 47 unsigned long omap1_uart_recalc(struct omap1_clk *clk, unsigned long p_rate) in omap1_uart_recalc() argument
49 unsigned int val = __raw_readl(clk->enable_reg); in omap1_uart_recalc()
50 return val & 1 << clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
53 unsigned long omap1_sossi_recalc(struct omap1_clk *clk, unsigned long p_rate) in omap1_sossi_recalc() argument
63 static void omap1_clk_allow_idle(struct omap1_clk *clk) in omap1_clk_allow_idle() argument
65 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_allow_idle()
67 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_allow_idle()
74 static void omap1_clk_deny_idle(struct omap1_clk *clk) in omap1_clk_deny_idle() argument
76 struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; in omap1_clk_deny_idle()
78 if (!(clk->flags & CLOCK_IDLE_CONTROL)) in omap1_clk_deny_idle()
[all …]
|
| /openbmc/linux/kernel/time/ |
| H A D | posix-clock.c | 22 struct posix_clock *clk = fp->private_data; in get_posix_clock() local
24 down_read(&clk->rwsem); in get_posix_clock()
26 if (!clk->zombie) in get_posix_clock()
27 return clk; in get_posix_clock()
29 up_read(&clk->rwsem); in get_posix_clock()
34 static void put_posix_clock(struct posix_clock *clk) in put_posix_clock() argument
36 up_read(&clk->rwsem); in put_posix_clock()
42 struct posix_clock *clk = get_posix_clock(fp); in posix_clock_read() local
45 if (!clk) in posix_clock_read()
48 if (clk->ops.read) in posix_clock_read()
[all …]
|