Lines Matching refs:clk
82 static struct clk *clk[clk_max]; variable
106 clk[ckih] = imx_clk_fixed("ckih", 24000000); in _mx35_clocks_init()
107 clk[ckil] = imx_clk_fixed("ckil", 32768); in _mx35_clocks_init()
108 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); in _mx35_clocks_init()
109 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); in _mx35_clocks_init()
111 clk[mpll] = imx_clk_fixed_factor("mpll_075", "mpll", 3, 4); in _mx35_clocks_init()
114 clk[arm] = imx_clk_fixed_factor("arm", "mpll_075", 1, aad->arm); in _mx35_clocks_init()
116 clk[arm] = imx_clk_fixed_factor("arm", "mpll", 1, aad->arm); in _mx35_clocks_init()
118 if (clk_get_rate(clk[arm]) > 400000000) in _mx35_clocks_init()
129 clk[hsp] = imx_clk_fixed_factor("hsp", "arm", 1, hsp_div[hsp_sel]); in _mx35_clocks_init()
131 clk[ahb] = imx_clk_fixed_factor("ahb", "arm", 1, aad->ahb); in _mx35_clocks_init()
132 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in _mx35_clocks_init()
134 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); in _mx35_clocks_init()
135 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); in _mx35_clocks_init()
136 …clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_… in _mx35_clocks_init()
138 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
139 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); in _mx35_clocks_init()
141 …clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)… in _mx35_clocks_init()
142 clk[esdhc1_div] = imx_clk_divider("esdhc1_div", "esdhc_sel", base + MX35_CCM_PDR3, 0, 6); in _mx35_clocks_init()
143 clk[esdhc2_div] = imx_clk_divider("esdhc2_div", "esdhc_sel", base + MX35_CCM_PDR3, 8, 6); in _mx35_clocks_init()
144 clk[esdhc3_div] = imx_clk_divider("esdhc3_div", "esdhc_sel", base + MX35_CCM_PDR3, 16, 6); in _mx35_clocks_init()
146 …clk[spdif_sel] = imx_clk_mux("spdif_sel", base + MX35_CCM_PDR3, 22, 1, std_sel, ARRAY_SIZE(std_sel… in _mx35_clocks_init()
147 …clk[spdif_div_pre] = imx_clk_divider("spdif_div_pre", "spdif_sel", base + MX35_CCM_PDR3, 29, 3); /… in _mx35_clocks_init()
148 …clk[spdif_div_post] = imx_clk_divider("spdif_div_post", "spdif_div_pre", base + MX35_CCM_PDR3, 23,… in _mx35_clocks_init()
150 clk[ssi_sel] = imx_clk_mux("ssi_sel", base + MX35_CCM_PDR2, 6, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
151 clk[ssi1_div_pre] = imx_clk_divider("ssi1_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 24, 3); in _mx35_clocks_init()
152 clk[ssi1_div_post] = imx_clk_divider("ssi1_div_post", "ssi1_div_pre", base + MX35_CCM_PDR2, 0, 6); in _mx35_clocks_init()
153 clk[ssi2_div_pre] = imx_clk_divider("ssi2_div_pre", "ssi_sel", base + MX35_CCM_PDR2, 27, 3); in _mx35_clocks_init()
154 clk[ssi2_div_post] = imx_clk_divider("ssi2_div_post", "ssi2_div_pre", base + MX35_CCM_PDR2, 8, 6); in _mx35_clocks_init()
156 clk[usb_sel] = imx_clk_mux("usb_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
157 clk[usb_div] = imx_clk_divider("usb_div", "usb_sel", base + MX35_CCM_PDR4, 22, 6); in _mx35_clocks_init()
159 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4); in _mx35_clocks_init()
161 clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel)); in _mx35_clocks_init()
162 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6); in _mx35_clocks_init()
164 clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0); in _mx35_clocks_init()
165 clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2); in _mx35_clocks_init()
166 clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4); in _mx35_clocks_init()
167 clk[can1_gate] = imx_clk_gate2("can1_gate", "ipg", base + MX35_CCM_CGR0, 6); in _mx35_clocks_init()
168 clk[can2_gate] = imx_clk_gate2("can2_gate", "ipg", base + MX35_CCM_CGR0, 8); in _mx35_clocks_init()
169 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MX35_CCM_CGR0, 10); in _mx35_clocks_init()
170 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MX35_CCM_CGR0, 12); in _mx35_clocks_init()
171 clk[ect_gate] = imx_clk_gate2("ect_gate", "ipg", base + MX35_CCM_CGR0, 14); in _mx35_clocks_init()
172 clk[edio_gate] = imx_clk_gate2("edio_gate", "ipg", base + MX35_CCM_CGR0, 16); in _mx35_clocks_init()
173 clk[emi_gate] = imx_clk_gate2("emi_gate", "ipg", base + MX35_CCM_CGR0, 18); in _mx35_clocks_init()
174 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "ipg", base + MX35_CCM_CGR0, 20); in _mx35_clocks_init()
175 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "ipg", base + MX35_CCM_CGR0, 22); in _mx35_clocks_init()
176 clk[esai_gate] = imx_clk_gate2("esai_gate", "ipg", base + MX35_CCM_CGR0, 24); in _mx35_clocks_init()
177 clk[esdhc1_gate] = imx_clk_gate2("esdhc1_gate", "esdhc1_div", base + MX35_CCM_CGR0, 26); in _mx35_clocks_init()
178 clk[esdhc2_gate] = imx_clk_gate2("esdhc2_gate", "esdhc2_div", base + MX35_CCM_CGR0, 28); in _mx35_clocks_init()
179 clk[esdhc3_gate] = imx_clk_gate2("esdhc3_gate", "esdhc3_div", base + MX35_CCM_CGR0, 30); in _mx35_clocks_init()
181 clk[fec_gate] = imx_clk_gate2("fec_gate", "ipg", base + MX35_CCM_CGR1, 0); in _mx35_clocks_init()
182 clk[gpio1_gate] = imx_clk_gate2("gpio1_gate", "ipg", base + MX35_CCM_CGR1, 2); in _mx35_clocks_init()
183 clk[gpio2_gate] = imx_clk_gate2("gpio2_gate", "ipg", base + MX35_CCM_CGR1, 4); in _mx35_clocks_init()
184 clk[gpio3_gate] = imx_clk_gate2("gpio3_gate", "ipg", base + MX35_CCM_CGR1, 6); in _mx35_clocks_init()
185 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "ipg", base + MX35_CCM_CGR1, 8); in _mx35_clocks_init()
186 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "ipg_per", base + MX35_CCM_CGR1, 10); in _mx35_clocks_init()
187 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "ipg_per", base + MX35_CCM_CGR1, 12); in _mx35_clocks_init()
188 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "ipg_per", base + MX35_CCM_CGR1, 14); in _mx35_clocks_init()
189 clk[iomuxc_gate] = imx_clk_gate2("iomuxc_gate", "ipg", base + MX35_CCM_CGR1, 16); in _mx35_clocks_init()
190 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MX35_CCM_CGR1, 18); in _mx35_clocks_init()
191 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MX35_CCM_CGR1, 20); in _mx35_clocks_init()
192 clk[mlb_gate] = imx_clk_gate2("mlb_gate", "ahb", base + MX35_CCM_CGR1, 22); in _mx35_clocks_init()
193 clk[mshc_gate] = imx_clk_gate2("mshc_gate", "dummy", base + MX35_CCM_CGR1, 24); in _mx35_clocks_init()
194 clk[owire_gate] = imx_clk_gate2("owire_gate", "ipg_per", base + MX35_CCM_CGR1, 26); in _mx35_clocks_init()
195 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "ipg_per", base + MX35_CCM_CGR1, 28); in _mx35_clocks_init()
196 clk[rngc_gate] = imx_clk_gate2("rngc_gate", "ipg", base + MX35_CCM_CGR1, 30); in _mx35_clocks_init()
198 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MX35_CCM_CGR2, 0); in _mx35_clocks_init()
199 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MX35_CCM_CGR2, 2); in _mx35_clocks_init()
200 clk[scc_gate] = imx_clk_gate2("scc_gate", "ipg", base + MX35_CCM_CGR2, 4); in _mx35_clocks_init()
201 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MX35_CCM_CGR2, 6); in _mx35_clocks_init()
202 clk[spba_gate] = imx_clk_gate2("spba_gate", "ipg", base + MX35_CCM_CGR2, 8); in _mx35_clocks_init()
203 clk[spdif_gate] = imx_clk_gate2("spdif_gate", "spdif_div_post", base + MX35_CCM_CGR2, 10); in _mx35_clocks_init()
204 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "ssi1_div_post", base + MX35_CCM_CGR2, 12); in _mx35_clocks_init()
205 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "ssi2_div_post", base + MX35_CCM_CGR2, 14); in _mx35_clocks_init()
206 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "uart_div", base + MX35_CCM_CGR2, 16); in _mx35_clocks_init()
207 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "uart_div", base + MX35_CCM_CGR2, 18); in _mx35_clocks_init()
208 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "uart_div", base + MX35_CCM_CGR2, 20); in _mx35_clocks_init()
209 clk[usbotg_gate] = imx_clk_gate2("usbotg_gate", "ahb", base + MX35_CCM_CGR2, 22); in _mx35_clocks_init()
210 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MX35_CCM_CGR2, 24); in _mx35_clocks_init()
211 clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26); in _mx35_clocks_init()
212 clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30); in _mx35_clocks_init()
214 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0); in _mx35_clocks_init()
215 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2); in _mx35_clocks_init()
216 clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4); in _mx35_clocks_init()
218 imx_check_clocks(clk, ARRAY_SIZE(clk)); in _mx35_clocks_init()
220 clk_prepare_enable(clk[spba_gate]); in _mx35_clocks_init()
221 clk_prepare_enable(clk[gpio1_gate]); in _mx35_clocks_init()
222 clk_prepare_enable(clk[gpio2_gate]); in _mx35_clocks_init()
223 clk_prepare_enable(clk[gpio3_gate]); in _mx35_clocks_init()
224 clk_prepare_enable(clk[iim_gate]); in _mx35_clocks_init()
225 clk_prepare_enable(clk[emi_gate]); in _mx35_clocks_init()
226 clk_prepare_enable(clk[max_gate]); in _mx35_clocks_init()
227 clk_prepare_enable(clk[iomuxc_gate]); in _mx35_clocks_init()
235 clk_prepare_enable(clk[scc_gate]); in _mx35_clocks_init()
246 clk_data.clks = clk; in mx35_clocks_init_dt()
247 clk_data.clk_num = ARRAY_SIZE(clk); in mx35_clocks_init_dt()