1f3867f43SBen Skeggs /*
2f3867f43SBen Skeggs * Copyright 2013 Red Hat Inc.
3f3867f43SBen Skeggs *
4f3867f43SBen Skeggs * Permission is hereby granted, free of charge, to any person obtaining a
5f3867f43SBen Skeggs * copy of this software and associated documentation files (the "Software"),
6f3867f43SBen Skeggs * to deal in the Software without restriction, including without limitation
7f3867f43SBen Skeggs * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8f3867f43SBen Skeggs * and/or sell copies of the Software, and to permit persons to whom the
9f3867f43SBen Skeggs * Software is furnished to do so, subject to the following conditions:
10f3867f43SBen Skeggs *
11f3867f43SBen Skeggs * The above copyright notice and this permission notice shall be included in
12f3867f43SBen Skeggs * all copies or substantial portions of the Software.
13f3867f43SBen Skeggs *
14f3867f43SBen Skeggs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15f3867f43SBen Skeggs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16f3867f43SBen Skeggs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17f3867f43SBen Skeggs * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18f3867f43SBen Skeggs * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19f3867f43SBen Skeggs * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20f3867f43SBen Skeggs * OTHER DEALINGS IN THE SOFTWARE.
21f3867f43SBen Skeggs *
22f3867f43SBen Skeggs * Authors: Ben Skeggs
23f3867f43SBen Skeggs */
246625f55cSBen Skeggs #include "priv.h"
256625f55cSBen Skeggs
26f3867f43SBen Skeggs #include <subdev/bios.h>
27f3867f43SBen Skeggs #include <subdev/bios/boost.h>
28f3867f43SBen Skeggs #include <subdev/bios/cstep.h>
29f3867f43SBen Skeggs #include <subdev/bios/perf.h>
304b9ce6e7SKarol Herbst #include <subdev/bios/vpstate.h>
317632b30eSBen Skeggs #include <subdev/fb.h>
327632b30eSBen Skeggs #include <subdev/therm.h>
337632b30eSBen Skeggs #include <subdev/volt.h>
347632b30eSBen Skeggs
357632b30eSBen Skeggs #include <core/option.h>
36f3867f43SBen Skeggs
37f3867f43SBen Skeggs /******************************************************************************
38f3867f43SBen Skeggs * misc
39f3867f43SBen Skeggs *****************************************************************************/
40f3867f43SBen Skeggs static u32
nvkm_clk_adjust(struct nvkm_clk * clk,bool adjust,u8 pstate,u8 domain,u32 input)417632b30eSBen Skeggs nvkm_clk_adjust(struct nvkm_clk *clk, bool adjust,
42f3867f43SBen Skeggs u8 pstate, u8 domain, u32 input)
43f3867f43SBen Skeggs {
4446484438SBen Skeggs struct nvkm_bios *bios = clk->subdev.device->bios;
45f3867f43SBen Skeggs struct nvbios_boostE boostE;
46f3867f43SBen Skeggs u8 ver, hdr, cnt, len;
4758786017SBen Skeggs u32 data;
48f3867f43SBen Skeggs
49f3867f43SBen Skeggs data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
50f3867f43SBen Skeggs if (data) {
51f3867f43SBen Skeggs struct nvbios_boostS boostS;
52f3867f43SBen Skeggs u8 idx = 0, sver, shdr;
5358786017SBen Skeggs u32 subd;
54f3867f43SBen Skeggs
55f3867f43SBen Skeggs input = max(boostE.min, input);
56f3867f43SBen Skeggs input = min(boostE.max, input);
57f3867f43SBen Skeggs do {
58f3867f43SBen Skeggs sver = ver;
59f3867f43SBen Skeggs shdr = hdr;
60f3867f43SBen Skeggs subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
61f3867f43SBen Skeggs cnt, len, &boostS);
62f3867f43SBen Skeggs if (subd && boostS.domain == domain) {
63f3867f43SBen Skeggs if (adjust)
64f3867f43SBen Skeggs input = input * boostS.percent / 100;
65f3867f43SBen Skeggs input = max(boostS.min, input);
66f3867f43SBen Skeggs input = min(boostS.max, input);
67f3867f43SBen Skeggs break;
68f3867f43SBen Skeggs }
69f3867f43SBen Skeggs } while (subd);
70f3867f43SBen Skeggs }
71f3867f43SBen Skeggs
72f3867f43SBen Skeggs return input;
73f3867f43SBen Skeggs }
74f3867f43SBen Skeggs
75f3867f43SBen Skeggs /******************************************************************************
76f3867f43SBen Skeggs * C-States
77f3867f43SBen Skeggs *****************************************************************************/
781f7f3d91SKarol Herbst static bool
nvkm_cstate_valid(struct nvkm_clk * clk,struct nvkm_cstate * cstate,u32 max_volt,int temp)791f7f3d91SKarol Herbst nvkm_cstate_valid(struct nvkm_clk *clk, struct nvkm_cstate *cstate,
801f7f3d91SKarol Herbst u32 max_volt, int temp)
811f7f3d91SKarol Herbst {
824b9ce6e7SKarol Herbst const struct nvkm_domain *domain = clk->domains;
831f7f3d91SKarol Herbst struct nvkm_volt *volt = clk->subdev.device->volt;
841f7f3d91SKarol Herbst int voltage;
851f7f3d91SKarol Herbst
864b9ce6e7SKarol Herbst while (domain && domain->name != nv_clk_src_max) {
874b9ce6e7SKarol Herbst if (domain->flags & NVKM_CLK_DOM_FLAG_VPSTATE) {
884b9ce6e7SKarol Herbst u32 freq = cstate->domain[domain->name];
894b9ce6e7SKarol Herbst switch (clk->boost_mode) {
904b9ce6e7SKarol Herbst case NVKM_CLK_BOOST_NONE:
914b9ce6e7SKarol Herbst if (clk->base_khz && freq > clk->base_khz)
924b9ce6e7SKarol Herbst return false;
93f6e7393eSGustavo A. R. Silva fallthrough;
944b9ce6e7SKarol Herbst case NVKM_CLK_BOOST_BIOS:
954b9ce6e7SKarol Herbst if (clk->boost_khz && freq > clk->boost_khz)
964b9ce6e7SKarol Herbst return false;
974b9ce6e7SKarol Herbst }
984b9ce6e7SKarol Herbst }
994b9ce6e7SKarol Herbst domain++;
1004b9ce6e7SKarol Herbst }
1014b9ce6e7SKarol Herbst
1021f7f3d91SKarol Herbst if (!volt)
1031f7f3d91SKarol Herbst return true;
1041f7f3d91SKarol Herbst
1051f7f3d91SKarol Herbst voltage = nvkm_volt_map(volt, cstate->voltage, temp);
1061f7f3d91SKarol Herbst if (voltage < 0)
1071f7f3d91SKarol Herbst return false;
1081f7f3d91SKarol Herbst return voltage <= min(max_volt, volt->max_uv);
1091f7f3d91SKarol Herbst }
1101f7f3d91SKarol Herbst
1111f7f3d91SKarol Herbst static struct nvkm_cstate *
nvkm_cstate_find_best(struct nvkm_clk * clk,struct nvkm_pstate * pstate,struct nvkm_cstate * cstate)1121f7f3d91SKarol Herbst nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate,
113dd3b89beSArushi Singhal struct nvkm_cstate *cstate)
1141f7f3d91SKarol Herbst {
1151f7f3d91SKarol Herbst struct nvkm_device *device = clk->subdev.device;
1161f7f3d91SKarol Herbst struct nvkm_volt *volt = device->volt;
1171f7f3d91SKarol Herbst int max_volt;
1181f7f3d91SKarol Herbst
119dd3b89beSArushi Singhal if (!pstate || !cstate)
1201f7f3d91SKarol Herbst return NULL;
1211f7f3d91SKarol Herbst
1221f7f3d91SKarol Herbst if (!volt)
123dd3b89beSArushi Singhal return cstate;
1241f7f3d91SKarol Herbst
1251f7f3d91SKarol Herbst max_volt = volt->max_uv;
1261f7f3d91SKarol Herbst if (volt->max0_id != 0xff)
1271f7f3d91SKarol Herbst max_volt = min(max_volt,
1281f7f3d91SKarol Herbst nvkm_volt_map(volt, volt->max0_id, clk->temp));
1291f7f3d91SKarol Herbst if (volt->max1_id != 0xff)
1301f7f3d91SKarol Herbst max_volt = min(max_volt,
1311f7f3d91SKarol Herbst nvkm_volt_map(volt, volt->max1_id, clk->temp));
1321f7f3d91SKarol Herbst if (volt->max2_id != 0xff)
1331f7f3d91SKarol Herbst max_volt = min(max_volt,
1341f7f3d91SKarol Herbst nvkm_volt_map(volt, volt->max2_id, clk->temp));
1351f7f3d91SKarol Herbst
136dd3b89beSArushi Singhal list_for_each_entry_from_reverse(cstate, &pstate->list, head) {
1371f7f3d91SKarol Herbst if (nvkm_cstate_valid(clk, cstate, max_volt, clk->temp))
1381c3b2a27SXiaomeng Tong return cstate;
1391f7f3d91SKarol Herbst }
1401f7f3d91SKarol Herbst
1411c3b2a27SXiaomeng Tong return NULL;
1421f7f3d91SKarol Herbst }
1431f7f3d91SKarol Herbst
1440d6f8100SKarol Herbst static struct nvkm_cstate *
nvkm_cstate_get(struct nvkm_clk * clk,struct nvkm_pstate * pstate,int cstatei)1450d6f8100SKarol Herbst nvkm_cstate_get(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
1460d6f8100SKarol Herbst {
1470d6f8100SKarol Herbst struct nvkm_cstate *cstate;
1480d6f8100SKarol Herbst if (cstatei == NVKM_CLK_CSTATE_HIGHEST)
1490d6f8100SKarol Herbst return list_last_entry(&pstate->list, typeof(*cstate), head);
1500d6f8100SKarol Herbst else {
1510d6f8100SKarol Herbst list_for_each_entry(cstate, &pstate->list, head) {
1520d6f8100SKarol Herbst if (cstate->id == cstatei)
1530d6f8100SKarol Herbst return cstate;
1540d6f8100SKarol Herbst }
1550d6f8100SKarol Herbst }
1560d6f8100SKarol Herbst return NULL;
1570d6f8100SKarol Herbst }
1580d6f8100SKarol Herbst
159f3867f43SBen Skeggs static int
nvkm_cstate_prog(struct nvkm_clk * clk,struct nvkm_pstate * pstate,int cstatei)1607632b30eSBen Skeggs nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
161f3867f43SBen Skeggs {
162b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->subdev;
163b907649eSBen Skeggs struct nvkm_device *device = subdev->device;
164b907649eSBen Skeggs struct nvkm_therm *therm = device->therm;
165b907649eSBen Skeggs struct nvkm_volt *volt = device->volt;
1667632b30eSBen Skeggs struct nvkm_cstate *cstate;
167f3867f43SBen Skeggs int ret;
168f3867f43SBen Skeggs
169f3867f43SBen Skeggs if (!list_empty(&pstate->list)) {
1700d6f8100SKarol Herbst cstate = nvkm_cstate_get(clk, pstate, cstatei);
1711f7f3d91SKarol Herbst cstate = nvkm_cstate_find_best(clk, pstate, cstate);
1721c3b2a27SXiaomeng Tong if (!cstate)
1731c3b2a27SXiaomeng Tong return -EINVAL;
174f3867f43SBen Skeggs } else {
175f3867f43SBen Skeggs cstate = &pstate->base;
176f3867f43SBen Skeggs }
177f3867f43SBen Skeggs
178da06b46bSBen Skeggs if (therm) {
179da06b46bSBen Skeggs ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
180f3867f43SBen Skeggs if (ret && ret != -ENODEV) {
181b907649eSBen Skeggs nvkm_error(subdev, "failed to raise fan speed: %d\n", ret);
182f3867f43SBen Skeggs return ret;
183f3867f43SBen Skeggs }
184f3867f43SBen Skeggs }
185f3867f43SBen Skeggs
186f3867f43SBen Skeggs if (volt) {
187fa6c4d8eSKarol Herbst ret = nvkm_volt_set_id(volt, cstate->voltage,
1888d08c264SKarol Herbst pstate->base.voltage, clk->temp, +1);
189f3867f43SBen Skeggs if (ret && ret != -ENODEV) {
190b907649eSBen Skeggs nvkm_error(subdev, "failed to raise voltage: %d\n", ret);
191f3867f43SBen Skeggs return ret;
192f3867f43SBen Skeggs }
193f3867f43SBen Skeggs }
194f3867f43SBen Skeggs
1956625f55cSBen Skeggs ret = clk->func->calc(clk, cstate);
196f3867f43SBen Skeggs if (ret == 0) {
1976625f55cSBen Skeggs ret = clk->func->prog(clk);
1986625f55cSBen Skeggs clk->func->tidy(clk);
199f3867f43SBen Skeggs }
200f3867f43SBen Skeggs
201f3867f43SBen Skeggs if (volt) {
202fa6c4d8eSKarol Herbst ret = nvkm_volt_set_id(volt, cstate->voltage,
2038d08c264SKarol Herbst pstate->base.voltage, clk->temp, -1);
204f3867f43SBen Skeggs if (ret && ret != -ENODEV)
205b907649eSBen Skeggs nvkm_error(subdev, "failed to lower voltage: %d\n", ret);
206f3867f43SBen Skeggs }
207f3867f43SBen Skeggs
208da06b46bSBen Skeggs if (therm) {
209da06b46bSBen Skeggs ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
210f3867f43SBen Skeggs if (ret && ret != -ENODEV)
211b907649eSBen Skeggs nvkm_error(subdev, "failed to lower fan speed: %d\n", ret);
212f3867f43SBen Skeggs }
213f3867f43SBen Skeggs
2143eca809bSBen Skeggs return ret;
215f3867f43SBen Skeggs }
216f3867f43SBen Skeggs
217f3867f43SBen Skeggs static void
nvkm_cstate_del(struct nvkm_cstate * cstate)2187632b30eSBen Skeggs nvkm_cstate_del(struct nvkm_cstate *cstate)
219f3867f43SBen Skeggs {
220f3867f43SBen Skeggs list_del(&cstate->head);
221f3867f43SBen Skeggs kfree(cstate);
222f3867f43SBen Skeggs }
223f3867f43SBen Skeggs
224f3867f43SBen Skeggs static int
nvkm_cstate_new(struct nvkm_clk * clk,int idx,struct nvkm_pstate * pstate)2257632b30eSBen Skeggs nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
226f3867f43SBen Skeggs {
22746484438SBen Skeggs struct nvkm_bios *bios = clk->subdev.device->bios;
22817d063dbSKarol Herbst struct nvkm_volt *volt = clk->subdev.device->volt;
2296625f55cSBen Skeggs const struct nvkm_domain *domain = clk->domains;
2307632b30eSBen Skeggs struct nvkm_cstate *cstate = NULL;
231f3867f43SBen Skeggs struct nvbios_cstepX cstepX;
232f3867f43SBen Skeggs u8 ver, hdr;
2336496b4e5SBen Skeggs u32 data;
234f3867f43SBen Skeggs
235f3867f43SBen Skeggs data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
236f3867f43SBen Skeggs if (!data)
237f3867f43SBen Skeggs return -ENOENT;
238f3867f43SBen Skeggs
23917d063dbSKarol Herbst if (volt && nvkm_volt_map_min(volt, cstepX.voltage) > volt->max_uv)
24017d063dbSKarol Herbst return -EINVAL;
24117d063dbSKarol Herbst
242f3867f43SBen Skeggs cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
243f3867f43SBen Skeggs if (!cstate)
244f3867f43SBen Skeggs return -ENOMEM;
245f3867f43SBen Skeggs
246f3867f43SBen Skeggs *cstate = pstate->base;
247f3867f43SBen Skeggs cstate->voltage = cstepX.voltage;
248761c8f69SKarol Herbst cstate->id = idx;
249f3867f43SBen Skeggs
250f3867f43SBen Skeggs while (domain && domain->name != nv_clk_src_max) {
251f3867f43SBen Skeggs if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
2527632b30eSBen Skeggs u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
2537632b30eSBen Skeggs domain->bios, cstepX.freq);
254f3867f43SBen Skeggs cstate->domain[domain->name] = freq;
255f3867f43SBen Skeggs }
256f3867f43SBen Skeggs domain++;
257f3867f43SBen Skeggs }
258f3867f43SBen Skeggs
259f3867f43SBen Skeggs list_add(&cstate->head, &pstate->list);
260f3867f43SBen Skeggs return 0;
261f3867f43SBen Skeggs }
262f3867f43SBen Skeggs
263f3867f43SBen Skeggs /******************************************************************************
264f3867f43SBen Skeggs * P-States
265f3867f43SBen Skeggs *****************************************************************************/
266f3867f43SBen Skeggs static int
nvkm_pstate_prog(struct nvkm_clk * clk,int pstatei)2677632b30eSBen Skeggs nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
268f3867f43SBen Skeggs {
269b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->subdev;
270cc90baddSKarol Herbst struct nvkm_fb *fb = subdev->device->fb;
271f68f4c96SKarol Herbst struct nvkm_pci *pci = subdev->device->pci;
2727632b30eSBen Skeggs struct nvkm_pstate *pstate;
273f3867f43SBen Skeggs int ret, idx = 0;
274f3867f43SBen Skeggs
275f3867f43SBen Skeggs list_for_each_entry(pstate, &clk->states, head) {
276f3867f43SBen Skeggs if (idx++ == pstatei)
277f3867f43SBen Skeggs break;
278f3867f43SBen Skeggs }
279f3867f43SBen Skeggs
280b907649eSBen Skeggs nvkm_debug(subdev, "setting performance state %d\n", pstatei);
281f3867f43SBen Skeggs clk->pstate = pstatei;
282f3867f43SBen Skeggs
283f68f4c96SKarol Herbst nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width);
284f68f4c96SKarol Herbst
285cc90baddSKarol Herbst if (fb && fb->ram && fb->ram->func->calc) {
286cc90baddSKarol Herbst struct nvkm_ram *ram = fb->ram;
287f3867f43SBen Skeggs int khz = pstate->base.domain[nv_clk_src_mem];
288f3867f43SBen Skeggs do {
289d36a99d2SBen Skeggs ret = ram->func->calc(ram, khz);
290f3867f43SBen Skeggs if (ret == 0)
291d36a99d2SBen Skeggs ret = ram->func->prog(ram);
292f3867f43SBen Skeggs } while (ret > 0);
293d36a99d2SBen Skeggs ram->func->tidy(ram);
294f3867f43SBen Skeggs }
295f3867f43SBen Skeggs
2960d6f8100SKarol Herbst return nvkm_cstate_prog(clk, pstate, NVKM_CLK_CSTATE_HIGHEST);
297f3867f43SBen Skeggs }
298f3867f43SBen Skeggs
299f3867f43SBen Skeggs static void
nvkm_pstate_work(struct work_struct * work)3007632b30eSBen Skeggs nvkm_pstate_work(struct work_struct *work)
301f3867f43SBen Skeggs {
3027632b30eSBen Skeggs struct nvkm_clk *clk = container_of(work, typeof(*clk), work);
303b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->subdev;
304f3867f43SBen Skeggs int pstate;
305f3867f43SBen Skeggs
306f3867f43SBen Skeggs if (!atomic_xchg(&clk->waiting, 0))
307f3867f43SBen Skeggs return;
308f3867f43SBen Skeggs clk->pwrsrc = power_supply_is_system_supplied();
309f3867f43SBen Skeggs
31061a8b84fSKarol Herbst nvkm_trace(subdev, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d°C D %d\n",
311f3867f43SBen Skeggs clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
31261a8b84fSKarol Herbst clk->astate, clk->temp, clk->dstate);
313f3867f43SBen Skeggs
314f3867f43SBen Skeggs pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
315f3867f43SBen Skeggs if (clk->state_nr && pstate != -1) {
316f3867f43SBen Skeggs pstate = (pstate < 0) ? clk->astate : pstate;
31761a8b84fSKarol Herbst pstate = min(pstate, clk->state_nr - 1);
318f3867f43SBen Skeggs pstate = max(pstate, clk->dstate);
319f3867f43SBen Skeggs } else {
320f3867f43SBen Skeggs pstate = clk->pstate = -1;
321f3867f43SBen Skeggs }
322f3867f43SBen Skeggs
323b907649eSBen Skeggs nvkm_trace(subdev, "-> %d\n", pstate);
324f3867f43SBen Skeggs if (pstate != clk->pstate) {
3257632b30eSBen Skeggs int ret = nvkm_pstate_prog(clk, pstate);
326f3867f43SBen Skeggs if (ret) {
327b907649eSBen Skeggs nvkm_error(subdev, "error setting pstate %d: %d\n",
328f3867f43SBen Skeggs pstate, ret);
329f3867f43SBen Skeggs }
330f3867f43SBen Skeggs }
331f3867f43SBen Skeggs
332f3867f43SBen Skeggs wake_up_all(&clk->wait);
333f3867f43SBen Skeggs }
334f3867f43SBen Skeggs
335f3867f43SBen Skeggs static int
nvkm_pstate_calc(struct nvkm_clk * clk,bool wait)3367632b30eSBen Skeggs nvkm_pstate_calc(struct nvkm_clk *clk, bool wait)
337f3867f43SBen Skeggs {
338f3867f43SBen Skeggs atomic_set(&clk->waiting, 1);
339f3867f43SBen Skeggs schedule_work(&clk->work);
340f3867f43SBen Skeggs if (wait)
341f3867f43SBen Skeggs wait_event(clk->wait, !atomic_read(&clk->waiting));
342f3867f43SBen Skeggs return 0;
343f3867f43SBen Skeggs }
344f3867f43SBen Skeggs
345f3867f43SBen Skeggs static void
nvkm_pstate_info(struct nvkm_clk * clk,struct nvkm_pstate * pstate)3467632b30eSBen Skeggs nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
347f3867f43SBen Skeggs {
3486625f55cSBen Skeggs const struct nvkm_domain *clock = clk->domains - 1;
3497632b30eSBen Skeggs struct nvkm_cstate *cstate;
350b907649eSBen Skeggs struct nvkm_subdev *subdev = &clk->subdev;
351f3867f43SBen Skeggs char info[3][32] = { "", "", "" };
352f3867f43SBen Skeggs char name[4] = "--";
353f3867f43SBen Skeggs int i = -1;
354f3867f43SBen Skeggs
355f3867f43SBen Skeggs if (pstate->pstate != 0xff)
356f3867f43SBen Skeggs snprintf(name, sizeof(name), "%02x", pstate->pstate);
357f3867f43SBen Skeggs
358f3867f43SBen Skeggs while ((++clock)->name != nv_clk_src_max) {
359f3867f43SBen Skeggs u32 lo = pstate->base.domain[clock->name];
360f3867f43SBen Skeggs u32 hi = lo;
361f3867f43SBen Skeggs if (hi == 0)
362f3867f43SBen Skeggs continue;
363f3867f43SBen Skeggs
364b907649eSBen Skeggs nvkm_debug(subdev, "%02x: %10d KHz\n", clock->name, lo);
365f3867f43SBen Skeggs list_for_each_entry(cstate, &pstate->list, head) {
366f3867f43SBen Skeggs u32 freq = cstate->domain[clock->name];
367f3867f43SBen Skeggs lo = min(lo, freq);
368f3867f43SBen Skeggs hi = max(hi, freq);
369b907649eSBen Skeggs nvkm_debug(subdev, "%10d KHz\n", freq);
370f3867f43SBen Skeggs }
371f3867f43SBen Skeggs
372f3867f43SBen Skeggs if (clock->mname && ++i < ARRAY_SIZE(info)) {
373f3867f43SBen Skeggs lo /= clock->mdiv;
374f3867f43SBen Skeggs hi /= clock->mdiv;
375f3867f43SBen Skeggs if (lo == hi) {
376f3867f43SBen Skeggs snprintf(info[i], sizeof(info[i]), "%s %d MHz",
377f3867f43SBen Skeggs clock->mname, lo);
378f3867f43SBen Skeggs } else {
379f3867f43SBen Skeggs snprintf(info[i], sizeof(info[i]),
380f3867f43SBen Skeggs "%s %d-%d MHz", clock->mname, lo, hi);
381f3867f43SBen Skeggs }
382f3867f43SBen Skeggs }
383f3867f43SBen Skeggs }
384f3867f43SBen Skeggs
385b907649eSBen Skeggs nvkm_debug(subdev, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
386f3867f43SBen Skeggs }
387f3867f43SBen Skeggs
388f3867f43SBen Skeggs static void
nvkm_pstate_del(struct nvkm_pstate * pstate)3897632b30eSBen Skeggs nvkm_pstate_del(struct nvkm_pstate *pstate)
390f3867f43SBen Skeggs {
3917632b30eSBen Skeggs struct nvkm_cstate *cstate, *temp;
392f3867f43SBen Skeggs
393f3867f43SBen Skeggs list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
3947632b30eSBen Skeggs nvkm_cstate_del(cstate);
395f3867f43SBen Skeggs }
396f3867f43SBen Skeggs
397f3867f43SBen Skeggs list_del(&pstate->head);
398f3867f43SBen Skeggs kfree(pstate);
399f3867f43SBen Skeggs }
400f3867f43SBen Skeggs
401f3867f43SBen Skeggs static int
nvkm_pstate_new(struct nvkm_clk * clk,int idx)4027632b30eSBen Skeggs nvkm_pstate_new(struct nvkm_clk *clk, int idx)
403f3867f43SBen Skeggs {
40446484438SBen Skeggs struct nvkm_bios *bios = clk->subdev.device->bios;
4056625f55cSBen Skeggs const struct nvkm_domain *domain = clk->domains - 1;
4067632b30eSBen Skeggs struct nvkm_pstate *pstate;
4077632b30eSBen Skeggs struct nvkm_cstate *cstate;
408f3867f43SBen Skeggs struct nvbios_cstepE cstepE;
409f3867f43SBen Skeggs struct nvbios_perfE perfE;
410f3867f43SBen Skeggs u8 ver, hdr, cnt, len;
4116496b4e5SBen Skeggs u32 data;
412f3867f43SBen Skeggs
413f3867f43SBen Skeggs data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
414f3867f43SBen Skeggs if (!data)
415f3867f43SBen Skeggs return -EINVAL;
416f3867f43SBen Skeggs if (perfE.pstate == 0xff)
417f3867f43SBen Skeggs return 0;
418f3867f43SBen Skeggs
419f3867f43SBen Skeggs pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
420f3867f43SBen Skeggs if (!pstate)
421f3867f43SBen Skeggs return -ENOMEM;
422f3867f43SBen Skeggs
423f3867f43SBen Skeggs INIT_LIST_HEAD(&pstate->list);
424f3867f43SBen Skeggs
425f3867f43SBen Skeggs pstate->pstate = perfE.pstate;
426f3867f43SBen Skeggs pstate->fanspeed = perfE.fanspeed;
427d3b378c0SKarol Herbst pstate->pcie_speed = perfE.pcie_speed;
428d3b378c0SKarol Herbst pstate->pcie_width = perfE.pcie_width;
429*41239aa4SMarkus Elfring cstate = &pstate->base;
430f3867f43SBen Skeggs cstate->voltage = perfE.voltage;
431f3867f43SBen Skeggs cstate->domain[nv_clk_src_core] = perfE.core;
432f3867f43SBen Skeggs cstate->domain[nv_clk_src_shader] = perfE.shader;
433f3867f43SBen Skeggs cstate->domain[nv_clk_src_mem] = perfE.memory;
434f3867f43SBen Skeggs cstate->domain[nv_clk_src_vdec] = perfE.vdec;
435f3867f43SBen Skeggs cstate->domain[nv_clk_src_dom6] = perfE.disp;
436f3867f43SBen Skeggs
437f3867f43SBen Skeggs while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
438f3867f43SBen Skeggs struct nvbios_perfS perfS;
439f3867f43SBen Skeggs u8 sver = ver, shdr = hdr;
440f3867f43SBen Skeggs u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
441f3867f43SBen Skeggs &sver, &shdr, cnt, len, &perfS);
442f3867f43SBen Skeggs if (perfSe == 0 || sver != 0x40)
443f3867f43SBen Skeggs continue;
444f3867f43SBen Skeggs
445f3867f43SBen Skeggs if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
4467632b30eSBen Skeggs perfS.v40.freq = nvkm_clk_adjust(clk, false,
447f3867f43SBen Skeggs pstate->pstate,
448f3867f43SBen Skeggs domain->bios,
449f3867f43SBen Skeggs perfS.v40.freq);
450f3867f43SBen Skeggs }
451f3867f43SBen Skeggs
452f3867f43SBen Skeggs cstate->domain[domain->name] = perfS.v40.freq;
453f3867f43SBen Skeggs }
454f3867f43SBen Skeggs
455f3867f43SBen Skeggs data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
456f3867f43SBen Skeggs if (data) {
457f3867f43SBen Skeggs int idx = cstepE.index;
458f3867f43SBen Skeggs do {
4597632b30eSBen Skeggs nvkm_cstate_new(clk, idx, pstate);
460f3867f43SBen Skeggs } while(idx--);
461f3867f43SBen Skeggs }
462f3867f43SBen Skeggs
4637632b30eSBen Skeggs nvkm_pstate_info(clk, pstate);
464f3867f43SBen Skeggs list_add_tail(&pstate->head, &clk->states);
465f3867f43SBen Skeggs clk->state_nr++;
466f3867f43SBen Skeggs return 0;
467f3867f43SBen Skeggs }
468f3867f43SBen Skeggs
469f3867f43SBen Skeggs /******************************************************************************
470f3867f43SBen Skeggs * Adjustment triggers
471f3867f43SBen Skeggs *****************************************************************************/
472f3867f43SBen Skeggs static int
nvkm_clk_ustate_update(struct nvkm_clk * clk,int req)4737632b30eSBen Skeggs nvkm_clk_ustate_update(struct nvkm_clk *clk, int req)
474f3867f43SBen Skeggs {
4757632b30eSBen Skeggs struct nvkm_pstate *pstate;
476f3867f43SBen Skeggs int i = 0;
477f3867f43SBen Skeggs
478f3867f43SBen Skeggs if (!clk->allow_reclock)
479f3867f43SBen Skeggs return -ENOSYS;
480f3867f43SBen Skeggs
481f3867f43SBen Skeggs if (req != -1 && req != -2) {
482f3867f43SBen Skeggs list_for_each_entry(pstate, &clk->states, head) {
483f3867f43SBen Skeggs if (pstate->pstate == req)
484f3867f43SBen Skeggs break;
485f3867f43SBen Skeggs i++;
486f3867f43SBen Skeggs }
487f3867f43SBen Skeggs
488f3867f43SBen Skeggs if (pstate->pstate != req)
489f3867f43SBen Skeggs return -EINVAL;
490f3867f43SBen Skeggs req = i;
491f3867f43SBen Skeggs }
492f3867f43SBen Skeggs
493f3867f43SBen Skeggs return req + 2;
494f3867f43SBen Skeggs }
495f3867f43SBen Skeggs
496f3867f43SBen Skeggs static int
nvkm_clk_nstate(struct nvkm_clk * clk,const char * mode,int arglen)4977632b30eSBen Skeggs nvkm_clk_nstate(struct nvkm_clk *clk, const char *mode, int arglen)
498f3867f43SBen Skeggs {
499f3867f43SBen Skeggs int ret = 1;
500f3867f43SBen Skeggs
501f3867f43SBen Skeggs if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen))
502f3867f43SBen Skeggs return -2;
503f3867f43SBen Skeggs
504f3867f43SBen Skeggs if (strncasecmpz(mode, "disabled", arglen)) {
505f3867f43SBen Skeggs char save = mode[arglen];
506f3867f43SBen Skeggs long v;
507f3867f43SBen Skeggs
508f3867f43SBen Skeggs ((char *)mode)[arglen] = '\0';
509f3867f43SBen Skeggs if (!kstrtol(mode, 0, &v)) {
5107632b30eSBen Skeggs ret = nvkm_clk_ustate_update(clk, v);
511f3867f43SBen Skeggs if (ret < 0)
512f3867f43SBen Skeggs ret = 1;
513f3867f43SBen Skeggs }
514f3867f43SBen Skeggs ((char *)mode)[arglen] = save;
515f3867f43SBen Skeggs }
516f3867f43SBen Skeggs
517f3867f43SBen Skeggs return ret - 2;
518f3867f43SBen Skeggs }
519f3867f43SBen Skeggs
520f3867f43SBen Skeggs int
nvkm_clk_ustate(struct nvkm_clk * clk,int req,int pwr)5217632b30eSBen Skeggs nvkm_clk_ustate(struct nvkm_clk *clk, int req, int pwr)
522f3867f43SBen Skeggs {
5237632b30eSBen Skeggs int ret = nvkm_clk_ustate_update(clk, req);
524f3867f43SBen Skeggs if (ret >= 0) {
525f3867f43SBen Skeggs if (ret -= 2, pwr) clk->ustate_ac = ret;
526f3867f43SBen Skeggs else clk->ustate_dc = ret;
5277632b30eSBen Skeggs return nvkm_pstate_calc(clk, true);
528f3867f43SBen Skeggs }
529f3867f43SBen Skeggs return ret;
530f3867f43SBen Skeggs }
531f3867f43SBen Skeggs
532f3867f43SBen Skeggs int
nvkm_clk_astate(struct nvkm_clk * clk,int req,int rel,bool wait)5337632b30eSBen Skeggs nvkm_clk_astate(struct nvkm_clk *clk, int req, int rel, bool wait)
534f3867f43SBen Skeggs {
535f3867f43SBen Skeggs if (!rel) clk->astate = req;
536f3867f43SBen Skeggs if ( rel) clk->astate += rel;
537f3867f43SBen Skeggs clk->astate = min(clk->astate, clk->state_nr - 1);
538f3867f43SBen Skeggs clk->astate = max(clk->astate, 0);
5397632b30eSBen Skeggs return nvkm_pstate_calc(clk, wait);
540f3867f43SBen Skeggs }
541f3867f43SBen Skeggs
542f3867f43SBen Skeggs int
nvkm_clk_tstate(struct nvkm_clk * clk,u8 temp)54361a8b84fSKarol Herbst nvkm_clk_tstate(struct nvkm_clk *clk, u8 temp)
544f3867f43SBen Skeggs {
54561a8b84fSKarol Herbst if (clk->temp == temp)
54661a8b84fSKarol Herbst return 0;
54761a8b84fSKarol Herbst clk->temp = temp;
54861a8b84fSKarol Herbst return nvkm_pstate_calc(clk, false);
549f3867f43SBen Skeggs }
550f3867f43SBen Skeggs
551f3867f43SBen Skeggs int
nvkm_clk_dstate(struct nvkm_clk * clk,int req,int rel)5527632b30eSBen Skeggs nvkm_clk_dstate(struct nvkm_clk *clk, int req, int rel)
553f3867f43SBen Skeggs {
554f3867f43SBen Skeggs if (!rel) clk->dstate = req;
555f3867f43SBen Skeggs if ( rel) clk->dstate += rel;
556f3867f43SBen Skeggs clk->dstate = min(clk->dstate, clk->state_nr - 1);
557f3867f43SBen Skeggs clk->dstate = max(clk->dstate, 0);
5587632b30eSBen Skeggs return nvkm_pstate_calc(clk, true);
559f3867f43SBen Skeggs }
560f3867f43SBen Skeggs
5610196cc65SBen Skeggs int
nvkm_clk_pwrsrc(struct nvkm_device * device)5620196cc65SBen Skeggs nvkm_clk_pwrsrc(struct nvkm_device *device)
563f3867f43SBen Skeggs {
5640196cc65SBen Skeggs if (device->clk)
5650196cc65SBen Skeggs return nvkm_pstate_calc(device->clk, false);
5660196cc65SBen Skeggs return 0;
567f3867f43SBen Skeggs }
568f3867f43SBen Skeggs
569f3867f43SBen Skeggs /******************************************************************************
570f3867f43SBen Skeggs * subdev base class implementation
571f3867f43SBen Skeggs *****************************************************************************/
572f3867f43SBen Skeggs
573f3867f43SBen Skeggs int
nvkm_clk_read(struct nvkm_clk * clk,enum nv_clk_src src)5746625f55cSBen Skeggs nvkm_clk_read(struct nvkm_clk *clk, enum nv_clk_src src)
575f3867f43SBen Skeggs {
5766625f55cSBen Skeggs return clk->func->read(clk, src);
577f3867f43SBen Skeggs }
578f3867f43SBen Skeggs
5796625f55cSBen Skeggs static int
nvkm_clk_fini(struct nvkm_subdev * subdev,bool suspend)5806625f55cSBen Skeggs nvkm_clk_fini(struct nvkm_subdev *subdev, bool suspend)
581f3867f43SBen Skeggs {
5826625f55cSBen Skeggs struct nvkm_clk *clk = nvkm_clk(subdev);
5836625f55cSBen Skeggs flush_work(&clk->work);
5846625f55cSBen Skeggs if (clk->func->fini)
5856625f55cSBen Skeggs clk->func->fini(clk);
5866625f55cSBen Skeggs return 0;
5876625f55cSBen Skeggs }
588f3867f43SBen Skeggs
5896625f55cSBen Skeggs static int
nvkm_clk_init(struct nvkm_subdev * subdev)5906625f55cSBen Skeggs nvkm_clk_init(struct nvkm_subdev *subdev)
5916625f55cSBen Skeggs {
5926625f55cSBen Skeggs struct nvkm_clk *clk = nvkm_clk(subdev);
5936625f55cSBen Skeggs const struct nvkm_domain *clock = clk->domains;
5946625f55cSBen Skeggs int ret;
595f3867f43SBen Skeggs
596f3867f43SBen Skeggs memset(&clk->bstate, 0x00, sizeof(clk->bstate));
597f3867f43SBen Skeggs INIT_LIST_HEAD(&clk->bstate.list);
598f3867f43SBen Skeggs clk->bstate.pstate = 0xff;
599f3867f43SBen Skeggs
600f3867f43SBen Skeggs while (clock->name != nv_clk_src_max) {
6016625f55cSBen Skeggs ret = nvkm_clk_read(clk, clock->name);
602f3867f43SBen Skeggs if (ret < 0) {
603b907649eSBen Skeggs nvkm_error(subdev, "%02x freq unknown\n", clock->name);
604f3867f43SBen Skeggs return ret;
605f3867f43SBen Skeggs }
606f3867f43SBen Skeggs clk->bstate.base.domain[clock->name] = ret;
607f3867f43SBen Skeggs clock++;
608f3867f43SBen Skeggs }
609f3867f43SBen Skeggs
6107632b30eSBen Skeggs nvkm_pstate_info(clk, &clk->bstate);
611f3867f43SBen Skeggs
6126625f55cSBen Skeggs if (clk->func->init)
6136625f55cSBen Skeggs return clk->func->init(clk);
6146625f55cSBen Skeggs
615f3867f43SBen Skeggs clk->astate = clk->state_nr - 1;
616f3867f43SBen Skeggs clk->dstate = 0;
617f3867f43SBen Skeggs clk->pstate = -1;
61861a8b84fSKarol Herbst clk->temp = 90; /* reasonable default value */
6197632b30eSBen Skeggs nvkm_pstate_calc(clk, true);
620f3867f43SBen Skeggs return 0;
621f3867f43SBen Skeggs }
622f3867f43SBen Skeggs
6236625f55cSBen Skeggs static void *
nvkm_clk_dtor(struct nvkm_subdev * subdev)6246625f55cSBen Skeggs nvkm_clk_dtor(struct nvkm_subdev *subdev)
625f3867f43SBen Skeggs {
6266625f55cSBen Skeggs struct nvkm_clk *clk = nvkm_clk(subdev);
6277632b30eSBen Skeggs struct nvkm_pstate *pstate, *temp;
628f3867f43SBen Skeggs
6296625f55cSBen Skeggs /* Early return if the pstates have been provided statically */
6306625f55cSBen Skeggs if (clk->func->pstates)
6316625f55cSBen Skeggs return clk;
6326625f55cSBen Skeggs
633f3867f43SBen Skeggs list_for_each_entry_safe(pstate, temp, &clk->states, head) {
6347632b30eSBen Skeggs nvkm_pstate_del(pstate);
635f3867f43SBen Skeggs }
636f3867f43SBen Skeggs
6376625f55cSBen Skeggs return clk;
638f3867f43SBen Skeggs }
639f3867f43SBen Skeggs
6406625f55cSBen Skeggs static const struct nvkm_subdev_func
6416625f55cSBen Skeggs nvkm_clk = {
6426625f55cSBen Skeggs .dtor = nvkm_clk_dtor,
6436625f55cSBen Skeggs .init = nvkm_clk_init,
6446625f55cSBen Skeggs .fini = nvkm_clk_fini,
6456625f55cSBen Skeggs };
6466625f55cSBen Skeggs
647f3867f43SBen Skeggs int
nvkm_clk_ctor(const struct nvkm_clk_func * func,struct nvkm_device * device,enum nvkm_subdev_type type,int inst,bool allow_reclock,struct nvkm_clk * clk)6486625f55cSBen Skeggs nvkm_clk_ctor(const struct nvkm_clk_func *func, struct nvkm_device *device,
64998fd7f83SBen Skeggs enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk *clk)
650f3867f43SBen Skeggs {
6514b9ce6e7SKarol Herbst struct nvkm_subdev *subdev = &clk->subdev;
6524b9ce6e7SKarol Herbst struct nvkm_bios *bios = device->bios;
653f3867f43SBen Skeggs int ret, idx, arglen;
654f3867f43SBen Skeggs const char *mode;
6554b9ce6e7SKarol Herbst struct nvbios_vpstate_header h;
656f3867f43SBen Skeggs
65798fd7f83SBen Skeggs nvkm_subdev_ctor(&nvkm_clk, device, type, inst, subdev);
6584b9ce6e7SKarol Herbst
6594b9ce6e7SKarol Herbst if (bios && !nvbios_vpstate_parse(bios, &h)) {
6604b9ce6e7SKarol Herbst struct nvbios_vpstate_entry base, boost;
6614b9ce6e7SKarol Herbst if (!nvbios_vpstate_entry(bios, &h, h.boost_id, &boost))
6624b9ce6e7SKarol Herbst clk->boost_khz = boost.clock_mhz * 1000;
6634b9ce6e7SKarol Herbst if (!nvbios_vpstate_entry(bios, &h, h.base_id, &base))
6644b9ce6e7SKarol Herbst clk->base_khz = base.clock_mhz * 1000;
6654b9ce6e7SKarol Herbst }
6664b9ce6e7SKarol Herbst
6676625f55cSBen Skeggs clk->func = func;
668f3867f43SBen Skeggs INIT_LIST_HEAD(&clk->states);
6696625f55cSBen Skeggs clk->domains = func->domains;
670f3867f43SBen Skeggs clk->ustate_ac = -1;
671f3867f43SBen Skeggs clk->ustate_dc = -1;
6726625f55cSBen Skeggs clk->allow_reclock = allow_reclock;
673f3867f43SBen Skeggs
6747632b30eSBen Skeggs INIT_WORK(&clk->work, nvkm_pstate_work);
675f3867f43SBen Skeggs init_waitqueue_head(&clk->wait);
676f3867f43SBen Skeggs atomic_set(&clk->waiting, 0);
677f3867f43SBen Skeggs
678f3867f43SBen Skeggs /* If no pstates are provided, try and fetch them from the BIOS */
6796625f55cSBen Skeggs if (!func->pstates) {
680f3867f43SBen Skeggs idx = 0;
681f3867f43SBen Skeggs do {
6827632b30eSBen Skeggs ret = nvkm_pstate_new(clk, idx++);
683f3867f43SBen Skeggs } while (ret == 0);
684f3867f43SBen Skeggs } else {
6856625f55cSBen Skeggs for (idx = 0; idx < func->nr_pstates; idx++)
6866625f55cSBen Skeggs list_add_tail(&func->pstates[idx].head, &clk->states);
6876625f55cSBen Skeggs clk->state_nr = func->nr_pstates;
688f3867f43SBen Skeggs }
689f3867f43SBen Skeggs
6907632b30eSBen Skeggs mode = nvkm_stropt(device->cfgopt, "NvClkMode", &arglen);
691f3867f43SBen Skeggs if (mode) {
6927632b30eSBen Skeggs clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
6937632b30eSBen Skeggs clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
694f3867f43SBen Skeggs }
695f3867f43SBen Skeggs
6967632b30eSBen Skeggs mode = nvkm_stropt(device->cfgopt, "NvClkModeAC", &arglen);
697f3867f43SBen Skeggs if (mode)
6987632b30eSBen Skeggs clk->ustate_ac = nvkm_clk_nstate(clk, mode, arglen);
699f3867f43SBen Skeggs
7007632b30eSBen Skeggs mode = nvkm_stropt(device->cfgopt, "NvClkModeDC", &arglen);
701f3867f43SBen Skeggs if (mode)
7027632b30eSBen Skeggs clk->ustate_dc = nvkm_clk_nstate(clk, mode, arglen);
703f3867f43SBen Skeggs
7044b9ce6e7SKarol Herbst clk->boost_mode = nvkm_longopt(device->cfgopt, "NvBoost",
7054b9ce6e7SKarol Herbst NVKM_CLK_BOOST_NONE);
706f3867f43SBen Skeggs return 0;
707f3867f43SBen Skeggs }
7086625f55cSBen Skeggs
7096625f55cSBen Skeggs int
nvkm_clk_new_(const struct nvkm_clk_func * func,struct nvkm_device * device,enum nvkm_subdev_type type,int inst,bool allow_reclock,struct nvkm_clk ** pclk)7106625f55cSBen Skeggs nvkm_clk_new_(const struct nvkm_clk_func *func, struct nvkm_device *device,
71198fd7f83SBen Skeggs enum nvkm_subdev_type type, int inst, bool allow_reclock, struct nvkm_clk **pclk)
7126625f55cSBen Skeggs {
7136625f55cSBen Skeggs if (!(*pclk = kzalloc(sizeof(**pclk), GFP_KERNEL)))
7146625f55cSBen Skeggs return -ENOMEM;
71598fd7f83SBen Skeggs return nvkm_clk_ctor(func, device, type, inst, allow_reclock, *pclk);
7166625f55cSBen Skeggs }
717