13bb16560SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
25df33a62SViresh Kumar /*
35df33a62SViresh Kumar * SPEAr6xx machines clock framework source file
45df33a62SViresh Kumar *
55df33a62SViresh Kumar * Copyright (C) 2012 ST Microelectronics
6da89947bSViresh Kumar * Viresh Kumar <vireshk@kernel.org>
75df33a62SViresh Kumar */
85df33a62SViresh Kumar
95df33a62SViresh Kumar #include <linux/clkdev.h>
109afd20a5SViresh Kumar #include <linux/clk/spear.h>
115df33a62SViresh Kumar #include <linux/io.h>
125df33a62SViresh Kumar #include <linux/spinlock_types.h>
135df33a62SViresh Kumar #include "clk.h"
145df33a62SViresh Kumar
155df33a62SViresh Kumar static DEFINE_SPINLOCK(_lock);
165df33a62SViresh Kumar
17d9909ebeSArnd Bergmann #define PLL1_CTR (misc_base + 0x008)
18d9909ebeSArnd Bergmann #define PLL1_FRQ (misc_base + 0x00C)
19d9909ebeSArnd Bergmann #define PLL2_CTR (misc_base + 0x014)
20d9909ebeSArnd Bergmann #define PLL2_FRQ (misc_base + 0x018)
21d9909ebeSArnd Bergmann #define PLL_CLK_CFG (misc_base + 0x020)
225df33a62SViresh Kumar /* PLL_CLK_CFG register masks */
235df33a62SViresh Kumar #define MCTR_CLK_SHIFT 28
245df33a62SViresh Kumar #define MCTR_CLK_MASK 3
255df33a62SViresh Kumar
26d9909ebeSArnd Bergmann #define CORE_CLK_CFG (misc_base + 0x024)
275df33a62SViresh Kumar /* CORE CLK CFG register masks */
285df33a62SViresh Kumar #define HCLK_RATIO_SHIFT 10
295df33a62SViresh Kumar #define HCLK_RATIO_MASK 2
305df33a62SViresh Kumar #define PCLK_RATIO_SHIFT 8
315df33a62SViresh Kumar #define PCLK_RATIO_MASK 2
325df33a62SViresh Kumar
33d9909ebeSArnd Bergmann #define PERIP_CLK_CFG (misc_base + 0x028)
345df33a62SViresh Kumar /* PERIP_CLK_CFG register masks */
355df33a62SViresh Kumar #define CLCD_CLK_SHIFT 2
365df33a62SViresh Kumar #define CLCD_CLK_MASK 2
375df33a62SViresh Kumar #define UART_CLK_SHIFT 4
385df33a62SViresh Kumar #define UART_CLK_MASK 1
395df33a62SViresh Kumar #define FIRDA_CLK_SHIFT 5
405df33a62SViresh Kumar #define FIRDA_CLK_MASK 2
415df33a62SViresh Kumar #define GPT0_CLK_SHIFT 8
425df33a62SViresh Kumar #define GPT1_CLK_SHIFT 10
435df33a62SViresh Kumar #define GPT2_CLK_SHIFT 11
445df33a62SViresh Kumar #define GPT3_CLK_SHIFT 12
455df33a62SViresh Kumar #define GPT_CLK_MASK 1
465df33a62SViresh Kumar
47d9909ebeSArnd Bergmann #define PERIP1_CLK_ENB (misc_base + 0x02C)
485df33a62SViresh Kumar /* PERIP1_CLK_ENB register masks */
495df33a62SViresh Kumar #define UART0_CLK_ENB 3
505df33a62SViresh Kumar #define UART1_CLK_ENB 4
515df33a62SViresh Kumar #define SSP0_CLK_ENB 5
525df33a62SViresh Kumar #define SSP1_CLK_ENB 6
535df33a62SViresh Kumar #define I2C_CLK_ENB 7
545df33a62SViresh Kumar #define JPEG_CLK_ENB 8
555df33a62SViresh Kumar #define FSMC_CLK_ENB 9
565df33a62SViresh Kumar #define FIRDA_CLK_ENB 10
575df33a62SViresh Kumar #define GPT2_CLK_ENB 11
585df33a62SViresh Kumar #define GPT3_CLK_ENB 12
595df33a62SViresh Kumar #define GPIO2_CLK_ENB 13
605df33a62SViresh Kumar #define SSP2_CLK_ENB 14
615df33a62SViresh Kumar #define ADC_CLK_ENB 15
625df33a62SViresh Kumar #define GPT1_CLK_ENB 11
635df33a62SViresh Kumar #define RTC_CLK_ENB 17
645df33a62SViresh Kumar #define GPIO1_CLK_ENB 18
655df33a62SViresh Kumar #define DMA_CLK_ENB 19
665df33a62SViresh Kumar #define SMI_CLK_ENB 21
675df33a62SViresh Kumar #define CLCD_CLK_ENB 22
685df33a62SViresh Kumar #define GMAC_CLK_ENB 23
695df33a62SViresh Kumar #define USBD_CLK_ENB 24
705df33a62SViresh Kumar #define USBH0_CLK_ENB 25
715df33a62SViresh Kumar #define USBH1_CLK_ENB 26
725df33a62SViresh Kumar
73d9909ebeSArnd Bergmann #define PRSC0_CLK_CFG (misc_base + 0x044)
74d9909ebeSArnd Bergmann #define PRSC1_CLK_CFG (misc_base + 0x048)
75d9909ebeSArnd Bergmann #define PRSC2_CLK_CFG (misc_base + 0x04C)
765df33a62SViresh Kumar
77d9909ebeSArnd Bergmann #define CLCD_CLK_SYNT (misc_base + 0x05C)
78d9909ebeSArnd Bergmann #define FIRDA_CLK_SYNT (misc_base + 0x060)
79d9909ebeSArnd Bergmann #define UART_CLK_SYNT (misc_base + 0x064)
805df33a62SViresh Kumar
815df33a62SViresh Kumar /* vco rate configuration table, in ascending order of rates */
825df33a62SViresh Kumar static struct pll_rate_tbl pll_rtbl[] = {
835df33a62SViresh Kumar {.mode = 0, .m = 0x53, .n = 0x0F, .p = 0x1}, /* vco 332 & pll 166 MHz */
845df33a62SViresh Kumar {.mode = 0, .m = 0x85, .n = 0x0F, .p = 0x1}, /* vco 532 & pll 266 MHz */
855df33a62SViresh Kumar {.mode = 0, .m = 0xA6, .n = 0x0F, .p = 0x1}, /* vco 664 & pll 332 MHz */
865df33a62SViresh Kumar };
875df33a62SViresh Kumar
885df33a62SViresh Kumar /* aux rate configuration table, in ascending order of rates */
895df33a62SViresh Kumar static struct aux_rate_tbl aux_rtbl[] = {
905df33a62SViresh Kumar /* For PLL1 = 332 MHz */
91ef0fd0a2SDeepak Sikri {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
925df33a62SViresh Kumar {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
935df33a62SViresh Kumar {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
945df33a62SViresh Kumar {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
955df33a62SViresh Kumar };
965df33a62SViresh Kumar
97a8f4bf0eSVipul Kumar Samar static const char *clcd_parents[] = { "pll3_clk", "clcd_syn_gclk", };
98a8f4bf0eSVipul Kumar Samar static const char *firda_parents[] = { "pll3_clk", "firda_syn_gclk", };
99a8f4bf0eSVipul Kumar Samar static const char *uart_parents[] = { "pll3_clk", "uart_syn_gclk", };
100a8f4bf0eSVipul Kumar Samar static const char *gpt0_1_parents[] = { "pll3_clk", "gpt0_1_syn_clk", };
101a8f4bf0eSVipul Kumar Samar static const char *gpt2_parents[] = { "pll3_clk", "gpt2_syn_clk", };
102a8f4bf0eSVipul Kumar Samar static const char *gpt3_parents[] = { "pll3_clk", "gpt3_syn_clk", };
1035df33a62SViresh Kumar static const char *ddr_parents[] = { "ahb_clk", "ahbmult2_clk", "none",
1045df33a62SViresh Kumar "pll2_clk", };
1055df33a62SViresh Kumar
1065df33a62SViresh Kumar /* gpt rate configuration table, in ascending order of rates */
1075df33a62SViresh Kumar static struct gpt_rate_tbl gpt_rtbl[] = {
1085df33a62SViresh Kumar /* For pll1 = 332 MHz */
1095df33a62SViresh Kumar {.mscale = 4, .nscale = 0}, /* 41.5 MHz */
1105df33a62SViresh Kumar {.mscale = 2, .nscale = 0}, /* 55.3 MHz */
1115df33a62SViresh Kumar {.mscale = 1, .nscale = 0}, /* 83 MHz */
1125df33a62SViresh Kumar };
1135df33a62SViresh Kumar
spear6xx_clk_init(void __iomem * misc_base)114d9909ebeSArnd Bergmann void __init spear6xx_clk_init(void __iomem *misc_base)
1155df33a62SViresh Kumar {
1165df33a62SViresh Kumar struct clk *clk, *clk1;
1175df33a62SViresh Kumar
118afb4bdc9SStephen Boyd clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, 0, 32000);
1195df33a62SViresh Kumar clk_register_clkdev(clk, "osc_32k_clk", NULL);
1205df33a62SViresh Kumar
121afb4bdc9SStephen Boyd clk = clk_register_fixed_rate(NULL, "osc_30m_clk", NULL, 0, 30000000);
1225df33a62SViresh Kumar clk_register_clkdev(clk, "osc_30m_clk", NULL);
1235df33a62SViresh Kumar
1245df33a62SViresh Kumar /* clock derived from 32 KHz osc clk */
1255df33a62SViresh Kumar clk = clk_register_gate(NULL, "rtc_spear", "osc_32k_clk", 0,
1265df33a62SViresh Kumar PERIP1_CLK_ENB, RTC_CLK_ENB, 0, &_lock);
1275df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "rtc-spear");
1285df33a62SViresh Kumar
1295df33a62SViresh Kumar /* clock derived from 30 MHz osc clk */
130a8f4bf0eSVipul Kumar Samar clk = clk_register_fixed_rate(NULL, "pll3_clk", "osc_24m_clk", 0,
1315df33a62SViresh Kumar 48000000);
132a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "pll3_clk", NULL);
1335df33a62SViresh Kumar
1345df33a62SViresh Kumar clk = clk_register_vco_pll("vco1_clk", "pll1_clk", NULL, "osc_30m_clk",
1355df33a62SViresh Kumar 0, PLL1_CTR, PLL1_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
1365df33a62SViresh Kumar &_lock, &clk1, NULL);
1375df33a62SViresh Kumar clk_register_clkdev(clk, "vco1_clk", NULL);
1385df33a62SViresh Kumar clk_register_clkdev(clk1, "pll1_clk", NULL);
1395df33a62SViresh Kumar
140a8f4bf0eSVipul Kumar Samar clk = clk_register_vco_pll("vco2_clk", "pll2_clk", NULL, "osc_30m_clk",
141a8f4bf0eSVipul Kumar Samar 0, PLL2_CTR, PLL2_FRQ, pll_rtbl, ARRAY_SIZE(pll_rtbl),
142a8f4bf0eSVipul Kumar Samar &_lock, &clk1, NULL);
1435df33a62SViresh Kumar clk_register_clkdev(clk, "vco2_clk", NULL);
1445df33a62SViresh Kumar clk_register_clkdev(clk1, "pll2_clk", NULL);
1455df33a62SViresh Kumar
1465df33a62SViresh Kumar clk = clk_register_fixed_factor(NULL, "wdt_clk", "osc_30m_clk", 0, 1,
1475df33a62SViresh Kumar 1);
1481af897dfSQuentin Schulz clk_register_clkdev(clk, NULL, "fc880000.wdt");
1495df33a62SViresh Kumar
1505df33a62SViresh Kumar /* clock derived from pll1 clk */
15112499792SVipul Kumar Samar clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
15212499792SVipul Kumar Samar CLK_SET_RATE_PARENT, 1, 1);
1535df33a62SViresh Kumar clk_register_clkdev(clk, "cpu_clk", NULL);
1545df33a62SViresh Kumar
1555df33a62SViresh Kumar clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
1565df33a62SViresh Kumar CLK_SET_RATE_PARENT, CORE_CLK_CFG, HCLK_RATIO_SHIFT,
1575df33a62SViresh Kumar HCLK_RATIO_MASK, 0, &_lock);
1585df33a62SViresh Kumar clk_register_clkdev(clk, "ahb_clk", NULL);
1595df33a62SViresh Kumar
160a8f4bf0eSVipul Kumar Samar clk = clk_register_aux("uart_syn_clk", "uart_syn_gclk", "pll1_clk", 0,
161a8f4bf0eSVipul Kumar Samar UART_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
162a8f4bf0eSVipul Kumar Samar &_lock, &clk1);
163a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "uart_syn_clk", NULL);
164a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
1655df33a62SViresh Kumar
166a8f4bf0eSVipul Kumar Samar clk = clk_register_mux(NULL, "uart_mclk", uart_parents,
167819c1de3SJames Hogan ARRAY_SIZE(uart_parents), CLK_SET_RATE_NO_REPARENT,
168819c1de3SJames Hogan PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
169819c1de3SJames Hogan &_lock);
170a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "uart_mclk", NULL);
1715df33a62SViresh Kumar
172a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "uart0", "uart_mclk", 0, PERIP1_CLK_ENB,
173a8f4bf0eSVipul Kumar Samar UART0_CLK_ENB, 0, &_lock);
1745df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "d0000000.serial");
1755df33a62SViresh Kumar
176a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "uart1", "uart_mclk", 0, PERIP1_CLK_ENB,
177a8f4bf0eSVipul Kumar Samar UART1_CLK_ENB, 0, &_lock);
1785df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "d0080000.serial");
1795df33a62SViresh Kumar
180a8f4bf0eSVipul Kumar Samar clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk",
181a8f4bf0eSVipul Kumar Samar 0, FIRDA_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
182a8f4bf0eSVipul Kumar Samar &_lock, &clk1);
183a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "firda_syn_clk", NULL);
184a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
1855df33a62SViresh Kumar
186a8f4bf0eSVipul Kumar Samar clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
187819c1de3SJames Hogan ARRAY_SIZE(firda_parents), CLK_SET_RATE_NO_REPARENT,
188819c1de3SJames Hogan PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
189819c1de3SJames Hogan &_lock);
190a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "firda_mclk", NULL);
1915df33a62SViresh Kumar
192a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0,
1935df33a62SViresh Kumar PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock);
1945df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "firda");
1955df33a62SViresh Kumar
196a8f4bf0eSVipul Kumar Samar clk = clk_register_aux("clcd_syn_clk", "clcd_syn_gclk", "pll1_clk",
197a8f4bf0eSVipul Kumar Samar 0, CLCD_CLK_SYNT, NULL, aux_rtbl, ARRAY_SIZE(aux_rtbl),
198a8f4bf0eSVipul Kumar Samar &_lock, &clk1);
199a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "clcd_syn_clk", NULL);
200a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk1, "clcd_syn_gclk", NULL);
2015df33a62SViresh Kumar
202a8f4bf0eSVipul Kumar Samar clk = clk_register_mux(NULL, "clcd_mclk", clcd_parents,
203819c1de3SJames Hogan ARRAY_SIZE(clcd_parents), CLK_SET_RATE_NO_REPARENT,
204819c1de3SJames Hogan PERIP_CLK_CFG, CLCD_CLK_SHIFT, CLCD_CLK_MASK, 0,
205819c1de3SJames Hogan &_lock);
206a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "clcd_mclk", NULL);
2075df33a62SViresh Kumar
208a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "clcd_clk", "clcd_mclk", 0,
2095df33a62SViresh Kumar PERIP1_CLK_ENB, CLCD_CLK_ENB, 0, &_lock);
2109a856beeSKory Maincent clk_register_clkdev(clk, NULL, "fc200000.clcd");
2115df33a62SViresh Kumar
2125df33a62SViresh Kumar /* gpt clocks */
213a8f4bf0eSVipul Kumar Samar clk = clk_register_gpt("gpt0_1_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG,
2145df33a62SViresh Kumar gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
215a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "gpt0_1_syn_clk", NULL);
2165df33a62SViresh Kumar
217a8f4bf0eSVipul Kumar Samar clk = clk_register_mux(NULL, "gpt0_mclk", gpt0_1_parents,
218819c1de3SJames Hogan ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
219819c1de3SJames Hogan PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
2205df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "gpt0");
2215df33a62SViresh Kumar
222a8f4bf0eSVipul Kumar Samar clk = clk_register_mux(NULL, "gpt1_mclk", gpt0_1_parents,
223819c1de3SJames Hogan ARRAY_SIZE(gpt0_1_parents), CLK_SET_RATE_NO_REPARENT,
224819c1de3SJames Hogan PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
225a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "gpt1_mclk", NULL);
2265df33a62SViresh Kumar
227a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0,
2285df33a62SViresh Kumar PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock);
2295df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "gpt1");
2305df33a62SViresh Kumar
231a8f4bf0eSVipul Kumar Samar clk = clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG,
2325df33a62SViresh Kumar gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
233a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "gpt2_syn_clk", NULL);
2345df33a62SViresh Kumar
235a8f4bf0eSVipul Kumar Samar clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
236819c1de3SJames Hogan ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_NO_REPARENT,
237819c1de3SJames Hogan PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
238a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "gpt2_mclk", NULL);
2395df33a62SViresh Kumar
240a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0,
2415df33a62SViresh Kumar PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock);
2425df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "gpt2");
2435df33a62SViresh Kumar
244a8f4bf0eSVipul Kumar Samar clk = clk_register_gpt("gpt3_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG,
2455df33a62SViresh Kumar gpt_rtbl, ARRAY_SIZE(gpt_rtbl), &_lock);
246a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "gpt3_syn_clk", NULL);
2475df33a62SViresh Kumar
248a8f4bf0eSVipul Kumar Samar clk = clk_register_mux(NULL, "gpt3_mclk", gpt3_parents,
249819c1de3SJames Hogan ARRAY_SIZE(gpt3_parents), CLK_SET_RATE_NO_REPARENT,
250819c1de3SJames Hogan PERIP_CLK_CFG, GPT3_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
251a8f4bf0eSVipul Kumar Samar clk_register_clkdev(clk, "gpt3_mclk", NULL);
2525df33a62SViresh Kumar
253a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "gpt3_clk", "gpt3_mclk", 0,
2545df33a62SViresh Kumar PERIP1_CLK_ENB, GPT3_CLK_ENB, 0, &_lock);
2555df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "gpt3");
2565df33a62SViresh Kumar
2575df33a62SViresh Kumar /* clock derived from pll3 clk */
258a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
2595df33a62SViresh Kumar PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
260df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e1800000.ehci");
261df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e1900000.ohci");
2625df33a62SViresh Kumar
263a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
2645df33a62SViresh Kumar PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
265df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e2000000.ehci");
266df2449abSRajeev Kumar clk_register_clkdev(clk, NULL, "e2100000.ohci");
2675df33a62SViresh Kumar
268a8f4bf0eSVipul Kumar Samar clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
269a8f4bf0eSVipul Kumar Samar USBD_CLK_ENB, 0, &_lock);
2705df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "designware_udc");
2715df33a62SViresh Kumar
2725df33a62SViresh Kumar /* clock derived from ahb clk */
2735df33a62SViresh Kumar clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
2745df33a62SViresh Kumar 1);
2755df33a62SViresh Kumar clk_register_clkdev(clk, "ahbmult2_clk", NULL);
2765df33a62SViresh Kumar
2775df33a62SViresh Kumar clk = clk_register_mux(NULL, "ddr_clk", ddr_parents,
278819c1de3SJames Hogan ARRAY_SIZE(ddr_parents), CLK_SET_RATE_NO_REPARENT,
279819c1de3SJames Hogan PLL_CLK_CFG, MCTR_CLK_SHIFT, MCTR_CLK_MASK, 0, &_lock);
2805df33a62SViresh Kumar clk_register_clkdev(clk, "ddr_clk", NULL);
2815df33a62SViresh Kumar
2825df33a62SViresh Kumar clk = clk_register_divider(NULL, "apb_clk", "ahb_clk",
2835df33a62SViresh Kumar CLK_SET_RATE_PARENT, CORE_CLK_CFG, PCLK_RATIO_SHIFT,
2845df33a62SViresh Kumar PCLK_RATIO_MASK, 0, &_lock);
2855df33a62SViresh Kumar clk_register_clkdev(clk, "apb_clk", NULL);
2865df33a62SViresh Kumar
2875df33a62SViresh Kumar clk = clk_register_gate(NULL, "dma_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
2885df33a62SViresh Kumar DMA_CLK_ENB, 0, &_lock);
2895df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "fc400000.dma");
2905df33a62SViresh Kumar
2915df33a62SViresh Kumar clk = clk_register_gate(NULL, "fsmc_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
2925df33a62SViresh Kumar FSMC_CLK_ENB, 0, &_lock);
2935df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "d1800000.flash");
2945df33a62SViresh Kumar
2955df33a62SViresh Kumar clk = clk_register_gate(NULL, "gmac_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
2965df33a62SViresh Kumar GMAC_CLK_ENB, 0, &_lock);
2973a35fc3aSStefan Roese clk_register_clkdev(clk, NULL, "e0800000.ethernet");
2985df33a62SViresh Kumar
2995df33a62SViresh Kumar clk = clk_register_gate(NULL, "i2c_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
3005df33a62SViresh Kumar I2C_CLK_ENB, 0, &_lock);
3015df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "d0200000.i2c");
3025df33a62SViresh Kumar
3035df33a62SViresh Kumar clk = clk_register_gate(NULL, "jpeg_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
3045df33a62SViresh Kumar JPEG_CLK_ENB, 0, &_lock);
3055df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "jpeg");
3065df33a62SViresh Kumar
3075df33a62SViresh Kumar clk = clk_register_gate(NULL, "smi_clk", "ahb_clk", 0, PERIP1_CLK_ENB,
3085df33a62SViresh Kumar SMI_CLK_ENB, 0, &_lock);
3095df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "fc000000.flash");
3105df33a62SViresh Kumar
3115df33a62SViresh Kumar /* clock derived from apb clk */
3125df33a62SViresh Kumar clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
3135df33a62SViresh Kumar ADC_CLK_ENB, 0, &_lock);
3141b214013SThomas Petazzoni clk_register_clkdev(clk, NULL, "d820b000.adc");
3155df33a62SViresh Kumar
3165df33a62SViresh Kumar clk = clk_register_fixed_factor(NULL, "gpio0_clk", "apb_clk", 0, 1, 1);
3175df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "f0100000.gpio");
3185df33a62SViresh Kumar
3195df33a62SViresh Kumar clk = clk_register_gate(NULL, "gpio1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
3205df33a62SViresh Kumar GPIO1_CLK_ENB, 0, &_lock);
3215df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "fc980000.gpio");
3225df33a62SViresh Kumar
3235df33a62SViresh Kumar clk = clk_register_gate(NULL, "gpio2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
3245df33a62SViresh Kumar GPIO2_CLK_ENB, 0, &_lock);
3255df33a62SViresh Kumar clk_register_clkdev(clk, NULL, "d8100000.gpio");
3265df33a62SViresh Kumar
3275df33a62SViresh Kumar clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
3285df33a62SViresh Kumar SSP0_CLK_ENB, 0, &_lock);
329*5381dc78SKory Maincent clk_register_clkdev(clk, NULL, "d0100000.spi");
3305df33a62SViresh Kumar
3315df33a62SViresh Kumar clk = clk_register_gate(NULL, "ssp1_clk", "apb_clk", 0, PERIP1_CLK_ENB,
3325df33a62SViresh Kumar SSP1_CLK_ENB, 0, &_lock);
333*5381dc78SKory Maincent clk_register_clkdev(clk, NULL, "d0180000.spi");
3345df33a62SViresh Kumar
3355df33a62SViresh Kumar clk = clk_register_gate(NULL, "ssp2_clk", "apb_clk", 0, PERIP1_CLK_ENB,
3365df33a62SViresh Kumar SSP2_CLK_ENB, 0, &_lock);
337*5381dc78SKory Maincent clk_register_clkdev(clk, NULL, "d8180000.spi");
3385df33a62SViresh Kumar }
339