| /openbmc/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/ |
| H A D | math_support.h | 51 #define bit8(x) (bit4(x) | (bit4(x) >> 4)) macro
52 #define bit16(x) (bit8(x) | (bit8(x) >> 8))
|
| /openbmc/linux/include/uapi/linux/ |
| H A D | ioam6.h | 70 bit8:1, member
105 bit8:1, member
|
| /openbmc/libpldm/include/libpldm/ |
| H A D | pldm_types.h | 45 uint8_t bit8 : 1; member
67 uint8_t bit8 : 1; member
105 uint8_t bit8 : 1; member
|
| /openbmc/u-boot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 58 # bit8-7: TR2R
92 # bit8: 0, DLL reset=0 normal
115 # bit8 : 0
|
| /openbmc/u-boot/board/Marvell/dreamplug/ |
| H A D | kwbimage.cfg | 55 # bit8-7: TR2R
88 # bit8: 0, DLL reset=0 normal
110 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/Marvell/sheevaplug/ |
| H A D | kwbimage.cfg | 54 # bit8-7: TR2R
87 # bit8: 0, DLL reset=0 normal
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/Seagate/dockstar/ |
| H A D | kwbimage.cfg | 57 # bit8-7: TR2R
90 # bit8: 0, DLL reset=0 normal
112 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/Marvell/guruplug/ |
| H A D | kwbimage.cfg | 54 # bit8-7: TR2R
87 # bit8: 0, DLL reset=0 normal
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/Seagate/goflexhome/ |
| H A D | kwbimage.cfg | 60 # bit8-7: TR2R
93 # bit8: 0, DLL reset=0 normal
115 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/Synology/ds109/ |
| H A D | kwbimage.cfg | 58 # bit8-7: TR2R
91 # bit8: 0, DLL reset=0 normal
113 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/LaCie/netspace_v2/ |
| H A D | kwbimage-ns2l.cfg | 54 # bit8-7: TR2R
87 # bit8: 0, DLL reset=0 normal
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| H A D | kwbimage.cfg | 54 # bit8-7: TR2R
87 # bit8: 0, DLL reset=0 normal
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| H A D | kwbimage-is2.cfg | 54 # bit8-7: TR2R
87 # bit8: 0, DLL reset=0 normal
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/LaCie/net2big_v2/ |
| H A D | kwbimage.cfg | 54 # bit8-7: TR2R
87 # bit8: 0, DLL reset=0 normal
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/cloudengines/pogo_e02/ |
| H A D | kwbimage.cfg | 58 # bit8-7: TR2R
91 # bit8: 0, DLL reset=0 normal
113 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/Marvell/openrd/ |
| H A D | kwbimage.cfg | 54 # bit8-7: TR2R
87 # bit8: 0, DLL reset=0 normal
109 # bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/raidsonic/ib62x0/ |
| H A D | kwbimage.cfg | 55 # bit8-7: TR2R
88 # bit8: 0x0, DLL reset=0 normal
110 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/iomega/iconnect/ |
| H A D | kwbimage.cfg | 54 # bit8-7: TR2R
87 # bit8: 0x0, DLL reset=0 normal
109 # bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/buffalo/lsxl/ |
| H A D | kwbimage-lschl.cfg | 68 # bit8-7: 0, 1 cycle tR2R
105 # bit8: 0, (Reset DLL) Normal operation
129 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| H A D | kwbimage-lsxhl.cfg | 68 # bit8-7: 0, 1 cycle tR2R
105 # bit8: 0, (Reset DLL) Normal operation
129 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/d-link/dns325/ |
| H A D | kwbimage.cfg | 64 # bit8-7: 0, 1 cycle tR2R
97 # bit8: 0, (Reset DLL) Normal operation
119 # bit8: 1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
|
| /openbmc/u-boot/board/keymile/km_arm/ |
| H A D | kwbimage.cfg | 75 # bit8-7: TR2R
121 # bit8 : 0 , no sample stage
|
| H A D | kwbimage-memphis.cfg | 78 # bit8-7: TR2R
124 # bit8 : 1 , add a sample stage
|
| /openbmc/linux/Documentation/admin-guide/perf/ |
| H A D | hisi-pcie-pmu.rst | 66 lanes), bit8 is set, port=0x100; if these two Root Ports are both
|
| /openbmc/linux/tools/testing/selftests/net/ |
| H A D | ioam6_parser.c | 252 if (ioam6h->type.bit8) { in check_ioam6_data()
|