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/openbmc/qemu/tests/qtest/libqos/
H A Dvirtio-pci-modern.c19 return qpci_io_readb(dev->pdev, dev->bar, dev->device_cfg_offset + addr); in config_readb()
25 return qpci_io_readw(dev->pdev, dev->bar, dev->device_cfg_offset + addr); in config_readw()
31 return qpci_io_readl(dev->pdev, dev->bar, dev->device_cfg_offset + addr); in config_readl()
37 return qpci_io_readq(dev->pdev, dev->bar, dev->device_cfg_offset + addr); in config_readq()
45 qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + in get_features()
49 lo = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset + in get_features()
52 qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + in get_features()
56 hi = qpci_io_readl(dev->pdev, dev->bar, dev->common_cfg_offset + in get_features()
69 qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + in set_features()
73 qpci_io_writel(dev->pdev, dev->bar, dev->common_cfg_offset + in set_features()
[all …]
H A Dvirtio-pci.c45 return qpci_io_readb(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readb()
60 value = qpci_io_readw(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readw()
72 value = qpci_io_readl(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readl()
84 val = qpci_io_readq(dev->pdev, dev->bar, CONFIG_BASE(dev) + off); in qvirtio_pci_config_readq()
95 return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_HOST_FEATURES); in qvirtio_pci_get_features()
101 qpci_io_writel(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES, features); in qvirtio_pci_set_features()
107 return qpci_io_readl(dev->pdev, dev->bar, VIRTIO_PCI_GUEST_FEATURES); in qvirtio_pci_get_guest_features()
113 return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS); in qvirtio_pci_get_status()
119 qpci_io_writeb(dev->pdev, dev->bar, VIRTIO_PCI_STATUS, status); in qvirtio_pci_set_status()
143 return qpci_io_readb(dev->pdev, dev->bar, VIRTIO_PCI_ISR) & 1; in qvirtio_pci_get_queue_isr_status()
[all …]
H A Dusb.c19 void qusb_pci_init_one(QPCIBus *pcibus, struct qhc *hc, uint32_t devfn, int bar) in qusb_pci_init_one() argument
24 hc->bar = qpci_iomap(hc->dev, bar, NULL); in qusb_pci_init_one()
34 uint16_t value = qpci_io_readw(hc->dev, hc->bar, 0x10 + 2 * port); in uhci_port_test()
/openbmc/qemu/tests/qtest/
H A Dnvme-test.c54 QPCIBar bar; in nvmetest_oob_cmb_test() local
57 bar = qpci_iomap(pdev, 2, NULL); in nvmetest_oob_cmb_test()
59 qpci_io_writel(pdev, bar, 0, 0xccbbaa99); in nvmetest_oob_cmb_test()
60 g_assert_cmpint(qpci_io_readb(pdev, bar, 0), ==, 0x99); in nvmetest_oob_cmb_test()
61 g_assert_cmpint(qpci_io_readw(pdev, bar, 0), ==, 0xaa99); in nvmetest_oob_cmb_test()
64 qpci_io_writel(pdev, bar, cmb_bar_size - 1, 0x44332211); in nvmetest_oob_cmb_test()
65 g_assert_cmpint(qpci_io_readb(pdev, bar, cmb_bar_size - 1), ==, 0x11); in nvmetest_oob_cmb_test()
66 g_assert_cmpint(qpci_io_readw(pdev, bar, cmb_bar_size - 1), !=, 0x2211); in nvmetest_oob_cmb_test()
67 g_assert_cmpint(qpci_io_readl(pdev, bar, cmb_bar_size - 1), !=, 0x44332211); in nvmetest_oob_cmb_test()
74 QPCIBar bar; in nvmetest_reg_read_test() local
[all …]
H A Dpvpanic-pci-test.c29 QPCIBar bar; in test_panic_nopause() local
35 bar = qpci_iomap(dev, 0, NULL); in test_panic_nopause()
37 qpci_memread(dev, bar, 0, &val, sizeof(val)); in test_panic_nopause()
41 qpci_memwrite(dev, bar, 0, &val, sizeof(val)); in test_panic_nopause()
62 QPCIBar bar; in test_panic() local
68 bar = qpci_iomap(dev, 0, NULL); in test_panic()
70 qpci_memread(dev, bar, 0, &val, sizeof(val)); in test_panic()
74 qpci_memwrite(dev, bar, 0, &val, sizeof(val)); in test_panic()
95 QPCIBar bar; in test_pvshutdown() local
101 bar = qpci_iomap(dev, 0, NULL); in test_pvshutdown()
[all …]
H A Dtulip-test.c52 QPCIBar bar; in tulip_large_tx() local
59 bar = qpci_iomap(dev, 0, NULL); in tulip_large_tx()
71 qpci_io_writel(dev, bar, 0x20, context_pa); in tulip_large_tx()
72 qpci_io_writel(dev, bar, 0x30, CSR6_ST); in tulip_large_tx()
/openbmc/u-boot/doc/uImage.FIT/
H A Doverlay-fdt-boot.txt19 revisions, reva and revb. Assume that both board revisions can use add a bar
46 data = /incbin/("./foo-reva-bar.dtb");
51 data = /incbin/("./foo-revb-bar.dtb");
61 data = /incbin/("./foo-revb-bar-baz.dtb");
77 foo-reva-bar.dtb {
81 foo-revb-bar.dtb {
89 foo-revb-bar-baz.dtb {
105 foo-reva.dtb, foo-revb.dtb, foo-reva-bar.dtb, foo-revb-bar.dtb,
106 foo-revb-baz.dtb, foo-revb-bar-baz.dtb
147 data = /incbin/("./bar.dtbo");
[all …]
/openbmc/u-boot/drivers/misc/
H A Dswap_case.c24 u32 bar[6]; member
100 u32 *bar, result; in sandbox_swap_case_read_config() local
103 bar = &plat->bar[barnum]; in sandbox_swap_case_read_config()
105 result = *bar; in sandbox_swap_case_read_config()
106 if (*bar == 0xffffffff) { in sandbox_swap_case_read_config()
168 u32 *bar; in sandbox_swap_case_write_config() local
171 bar = &plat->bar[barnum]; in sandbox_swap_case_write_config()
174 *bar = value; in sandbox_swap_case_write_config()
176 *bar |= barinfo[barnum].type; in sandbox_swap_case_write_config()
192 u32 base = plat->bar[barnum] & ~PCI_BASE_ADDRESS_SPACE; in sandbox_swap_case_find_bar()
/openbmc/u-boot/drivers/pci/
H A Dpci_auto.c28 int bar, bar_nr = 0; in dm_pciauto_setup_device() local
40 for (bar = PCI_BASE_ADDRESS_0; in dm_pciauto_setup_device()
41 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { in dm_pciauto_setup_device()
44 dm_pci_write_config32(dev, bar, 0xffffffff); in dm_pciauto_setup_device()
45 dm_pci_read_config32(dev, bar, &bar_response); in dm_pciauto_setup_device()
69 dm_pci_write_config32(dev, bar + 4, in dm_pciauto_setup_device()
72 dm_pci_read_config32(dev, bar + 4, in dm_pciauto_setup_device()
104 dm_pci_write_config32(dev, bar, (u32)bar_value); in dm_pciauto_setup_device()
107 bar += 4; in dm_pciauto_setup_device()
109 dm_pci_write_config32(dev, bar, in dm_pciauto_setup_device()
[all …]
H A Dpci_auto_old.c37 int bar, bar_nr = 0; in pciauto_setup_device() local
50 for (bar = PCI_BASE_ADDRESS_0; in pciauto_setup_device()
51 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) { in pciauto_setup_device()
54 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); in pciauto_setup_device()
56 pci_hose_read_config_dword(hose, dev, bar, &bar_response); in pciauto_setup_device()
83 pci_hose_write_config_dword(hose, dev, bar + 4, in pciauto_setup_device()
86 pci_hose_read_config_dword(hose, dev, bar + 4, in pciauto_setup_device()
114 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value); in pciauto_setup_device()
117 bar += 4; in pciauto_setup_device()
119 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32)); in pciauto_setup_device()
[all …]
H A Dpci_common.c103 void *pci_map_bar(pci_dev_t pdev, int bar, int flags) in pci_map_bar() argument
109 pci_read_config_dword(pdev, bar, &bar_response); in pci_map_bar()
124 int bar; in pci_write_bar32() local
126 bar = PCI_BASE_ADDRESS_0 + barnum * 4; in pci_write_bar32()
127 pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl); in pci_write_bar32()
133 int bar; in pci_read_bar32() local
135 bar = PCI_BASE_ADDRESS_0 + barnum * 4; in pci_read_bar32()
136 pci_hose_read_config_dword(hose, dev, bar, &addr); in pci_read_bar32()
H A Dpci_ftpci100.c68 devs[priv->ndevs].bar[i].addr = priv->io_base; in setup_pci_bar()
69 devs[priv->ndevs].bar[i].size = size_mask + 1; in setup_pci_bar()
108 devs[priv->ndevs].bar[i].addr = alloc_base; in setup_pci_bar()
109 devs[priv->ndevs].bar[i].size = size_mask + 1; in setup_pci_bar()
113 devs[priv->ndevs].bar[0].addr, in setup_pci_bar()
114 devs[priv->ndevs].bar[0].size); in setup_pci_bar()
213 devs[priv->ndevs].bar[0].addr, in pci_bus_scan()
214 devs[priv->ndevs].bar[0].size, in pci_bus_scan()
H A Dpci.c195 int bar, found_mem64; in pci_hose_config_device() local
202 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) { in pci_hose_config_device()
203 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff); in pci_hose_config_device()
204 pci_hose_read_config_dword(hose, dev, bar, &bar_response); in pci_hose_config_device()
224 pci_hose_write_config_dword(hose, dev, bar + 4, in pci_hose_config_device()
226 pci_hose_read_config_dword(hose, dev, bar + 4, in pci_hose_config_device()
245 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value); in pci_hose_config_device()
248 bar += 4; in pci_hose_config_device()
250 pci_hose_write_config_dword(hose, dev, bar, in pci_hose_config_device()
253 pci_hose_write_config_dword(hose, dev, bar, 0x00000000); in pci_hose_config_device()
/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/
H A Dlaw.c28 ecm->bar = start & 0xfffff000; in set_ddr_laws()
30 debug("DDR:bar=0x%08x\n", ecm->bar); in set_ddr_laws()
45 ecm->bar = start & 0xfffff000; in set_ddr_laws()
47 debug("DDR:bar=0x%08x\n", ecm->bar); in set_ddr_laws()
/openbmc/qemu/hw/misc/macio/
H A Dmacio.c81 memory_region_add_subregion(&s->bar, 0x12000, escc_legacy); in macio_escc_legacy_setup()
87 MemoryRegion *bar = sysbus_mmio_get_region(sbd, 0); in macio_bar_setup() local
89 memory_region_add_subregion(&s->bar, 0x13000, bar); in macio_bar_setup()
102 memory_region_add_subregion(&s->bar, 0x08000, in macio_common_realize()
115 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar); in macio_common_realize()
155 memory_region_add_subregion(&s->bar, 0x0, in macio_oldworld_realize()
164 memory_region_add_subregion(&s->bar, 0x16000, in macio_oldworld_realize()
176 memory_region_add_subregion(&s->bar, 0x60000, in macio_oldworld_realize()
203 memory_region_add_subregion(&s->bar, addr, &ide->mem); in macio_init_ide()
278 memory_region_add_subregion(&s->bar, 0x40000, in macio_newworld_realize()
[all …]
/openbmc/phosphor-ipmi-flash/tools/
H A Dpci.cpp52 PciAccessBridge::PciAccessBridge(const struct pci_id_match* match, int bar, in PciAccessBridge() argument
69 if (!dev->regions[bar].is_IO) in PciAccessBridge()
81 std::fprintf(stderr, "bar%d[0x%x] \n", bar, in PciAccessBridge()
82 static_cast<unsigned int>(dev->regions[bar].base_addr)); in PciAccessBridge()
84 size = dev->regions[bar].size; in PciAccessBridge()
86 dev, dev->regions[bar].base_addr, dev->regions[bar].size, in PciAccessBridge()
H A Dpci.hpp67 PciAccessBridge(const struct pci_id_match* match, int bar,
88 PciAccessBridge(&match, bar, dataOffset, dataLength, pciAccess), in NuvotonPciBridge()
103 static constexpr int bar = 0; member in host_tool::NuvotonPciBridge
124 PciAccessBridge(&match, bar, dataOffset, dataLength, pciAccess), in AspeedPciBridge()
141 static constexpr int bar = 1; member in host_tool::AspeedPciBridge
/openbmc/bmcweb/test/redfish-core/include/
H A Dredfish_oem_routing_test.cpp34 const std::string& bar) { in TEST() argument
36 EXPECT_EQ(bar, "bar"); in TEST()
43 const std::string& bar) { in TEST() argument
46 EXPECT_EQ(bar, "bar"); in TEST()
121 const std::string& bar) { in TEST() argument
124 EXPECT_EQ(bar, "bar"); in TEST()
/openbmc/u-boot/board/freescale/mpc837xerdb/
H A Dpci.c78 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
81 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; in pci_init_board()
100 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); in pci_init_board()
103 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); in pci_init_board()
/openbmc/u-boot/arch/x86/cpu/quark/
H A Dquark.c298 u32 bar; in quark_usb_init() local
301 qrk_pci_read_config_dword(QUARK_USB_EHCI, PCI_BASE_ADDRESS_0, &bar); in quark_usb_init()
302 writel((0x7f << 16) | 0x7f, bar + EHCI_INSNREG01); in quark_usb_init()
305 qrk_pci_read_config_dword(QUARK_USB_DEVICE, PCI_BASE_ADDRESS_0, &bar); in quark_usb_init()
306 writel(0x7f, bar + USBD_INT_MASK); in quark_usb_init()
307 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_MASK); in quark_usb_init()
308 writel((0xf << 16) | 0xf, bar + USBD_EP_INT_STS); in quark_usb_init()
/openbmc/qemu/target/ppc/translate/
H A Dmisc-impl.c.inc26 TCGBar bar = TCG_MO_ALL;
38 tcg_gen_mb(bar | TCG_BAR_SC);
57 bar = TCG_MO_ST_ST;
61 bar = TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST;
77 tcg_gen_mb(bar | TCG_BAR_SC);
84 TCGBar bar = TCG_MO_ALL;
94 tcg_gen_mb(bar | TCG_BAR_SC);
140 bar = TCG_MO_ST_LD;
144 tcg_gen_mb(bar | TCG_BAR_SC);
/openbmc/qemu/hw/vfio/
H A Dpci.c1329 static void vfio_sub_page_bar_update_mapping(PCIDevice *pdev, int bar) in vfio_sub_page_bar_update_mapping() argument
1332 VFIORegion *region = &vdev->bars[bar].region; in vfio_sub_page_bar_update_mapping()
1344 r = &pdev->io_regions[bar]; in vfio_sub_page_bar_update_mapping()
1346 base_mr = vdev->bars[bar].mr; in vfio_sub_page_bar_update_mapping()
1358 if (vdev->bars[bar].size < size) { in vfio_sub_page_bar_update_mapping()
1363 if (size != vdev->bars[bar].size && memory_region_is_mapped(base_mr)) { in vfio_sub_page_bar_update_mapping()
1462 int bar; in vfio_pci_write_config() local
1464 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { in vfio_pci_write_config()
1465 old_addr[bar] = pdev->io_regions[bar].addr; in vfio_pci_write_config()
1470 for (bar = 0; bar < PCI_ROM_SLOT; bar++) { in vfio_pci_write_config()
[all …]
/openbmc/qemu/tests/tcg/x86_64/
H A Dtest-1648.c7 void bar(void) in bar() function
20 bar(); in foo()
/openbmc/u-boot/board/freescale/mpc837xemds/
H A Dpci.c96 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
99 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; in pci_init_board()
128 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); in pci_init_board()
131 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); in pci_init_board()
/openbmc/u-boot/board/freescale/mpc832xemds/
H A Dpci.c71 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
74 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; in pci_init_board()
129 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
132 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;

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