1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2e58fe957SKim Phillips /*
39993e196SKim Phillips * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4e58fe957SKim Phillips */
5e58fe957SKim Phillips
6e58fe957SKim Phillips /*
7e58fe957SKim Phillips * PCI Configuration space access support for MPC83xx PCI Bridge
8e58fe957SKim Phillips */
9e58fe957SKim Phillips #include <asm/mmu.h>
10e58fe957SKim Phillips #include <asm/io.h>
11e58fe957SKim Phillips #include <common.h>
129993e196SKim Phillips #include <mpc83xx.h>
13e58fe957SKim Phillips #include <pci.h>
14e58fe957SKim Phillips #include <i2c.h>
15e58fe957SKim Phillips #include <asm/fsl_i2c.h>
169993e196SKim Phillips #include "../common/pq-mds-pib.h"
17e58fe957SKim Phillips
189993e196SKim Phillips static struct pci_region pci1_regions[] = {
19e58fe957SKim Phillips {
209993e196SKim Phillips bus_start: CONFIG_SYS_PCI1_MEM_BASE,
219993e196SKim Phillips phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
229993e196SKim Phillips size: CONFIG_SYS_PCI1_MEM_SIZE,
239993e196SKim Phillips flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
24e58fe957SKim Phillips },
25e58fe957SKim Phillips {
269993e196SKim Phillips bus_start: CONFIG_SYS_PCI1_IO_BASE,
279993e196SKim Phillips phys_start: CONFIG_SYS_PCI1_IO_PHYS,
289993e196SKim Phillips size: CONFIG_SYS_PCI1_IO_SIZE,
299993e196SKim Phillips flags: PCI_REGION_IO
309993e196SKim Phillips },
319993e196SKim Phillips {
329993e196SKim Phillips bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
339993e196SKim Phillips phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
349993e196SKim Phillips size: CONFIG_SYS_PCI1_MMIO_SIZE,
359993e196SKim Phillips flags: PCI_REGION_MEM
36e58fe957SKim Phillips },
37e58fe957SKim Phillips };
38e58fe957SKim Phillips
399993e196SKim Phillips #ifdef CONFIG_MPC83XX_PCI2
409993e196SKim Phillips static struct pci_region pci2_regions[] = {
419993e196SKim Phillips {
429993e196SKim Phillips bus_start: CONFIG_SYS_PCI2_MEM_BASE,
439993e196SKim Phillips phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
449993e196SKim Phillips size: CONFIG_SYS_PCI2_MEM_SIZE,
459993e196SKim Phillips flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
469993e196SKim Phillips },
479993e196SKim Phillips {
489993e196SKim Phillips bus_start: CONFIG_SYS_PCI2_IO_BASE,
499993e196SKim Phillips phys_start: CONFIG_SYS_PCI2_IO_PHYS,
509993e196SKim Phillips size: CONFIG_SYS_PCI2_IO_SIZE,
519993e196SKim Phillips flags: PCI_REGION_IO
529993e196SKim Phillips },
539993e196SKim Phillips {
549993e196SKim Phillips bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
559993e196SKim Phillips phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
569993e196SKim Phillips size: CONFIG_SYS_PCI2_MMIO_SIZE,
579993e196SKim Phillips flags: PCI_REGION_MEM
589993e196SKim Phillips },
599993e196SKim Phillips };
609993e196SKim Phillips #endif
619993e196SKim Phillips
pci_init_board(void)62e58fe957SKim Phillips void pci_init_board(void)
63e58fe957SKim Phillips #ifdef CONFIG_PCISLAVE
64e58fe957SKim Phillips {
659993e196SKim Phillips volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
669993e196SKim Phillips volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
679993e196SKim Phillips volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
689993e196SKim Phillips struct pci_region *reg[] = { pci1_regions };
69e58fe957SKim Phillips
709993e196SKim Phillips /* Configure PCI Local Access Windows */
719993e196SKim Phillips pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
729993e196SKim Phillips pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
739993e196SKim Phillips
749993e196SKim Phillips pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
759993e196SKim Phillips pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
769993e196SKim Phillips
776aa3d3bfSPeter Tyser mpc83xx_pci_init(1, reg);
789993e196SKim Phillips
79e58fe957SKim Phillips /*
80e58fe957SKim Phillips * Configure PCI Inbound Translation Windows
81e58fe957SKim Phillips */
82e58fe957SKim Phillips pci_ctrl[0].pitar0 = 0x0;
83e58fe957SKim Phillips pci_ctrl[0].pibar0 = 0x0;
84e58fe957SKim Phillips pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
85e58fe957SKim Phillips PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
86e58fe957SKim Phillips
87e58fe957SKim Phillips pci_ctrl[0].pitar1 = 0x0;
88e58fe957SKim Phillips pci_ctrl[0].pibar1 = 0x0;
89e58fe957SKim Phillips pci_ctrl[0].piebar1 = 0x0;
90e58fe957SKim Phillips pci_ctrl[0].piwar1 &= ~PIWAR_EN;
91e58fe957SKim Phillips
92e58fe957SKim Phillips pci_ctrl[0].pitar2 = 0x0;
93e58fe957SKim Phillips pci_ctrl[0].pibar2 = 0x0;
94e58fe957SKim Phillips pci_ctrl[0].piebar2 = 0x0;
95e58fe957SKim Phillips pci_ctrl[0].piwar2 &= ~PIWAR_EN;
96e58fe957SKim Phillips
979993e196SKim Phillips /* Unlock the configuration bit */
989993e196SKim Phillips mpc83xx_pcislave_unlock(0);
999993e196SKim Phillips printf("PCI: Agent mode enabled\n");
100e58fe957SKim Phillips }
101e58fe957SKim Phillips #else
102e58fe957SKim Phillips {
1039993e196SKim Phillips volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
1049993e196SKim Phillips volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
1059993e196SKim Phillips volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
1069993e196SKim Phillips #ifndef CONFIG_MPC83XX_PCI2
1079993e196SKim Phillips struct pci_region *reg[] = { pci1_regions };
1089993e196SKim Phillips #else
1099993e196SKim Phillips struct pci_region *reg[] = { pci1_regions, pci2_regions };
1109993e196SKim Phillips #endif
111e58fe957SKim Phillips
1129993e196SKim Phillips /* initialize the PCA9555PW IO expander on the PIB board */
1139993e196SKim Phillips pib_init();
114e58fe957SKim Phillips
1152ae18241SWolfgang Denk #if defined(CONFIG_PCI_66M)
116e58fe957SKim Phillips clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
117e58fe957SKim Phillips printf("PCI clock is 66MHz\n");
1182ae18241SWolfgang Denk #elif defined(CONFIG_PCI_33M)
119e58fe957SKim Phillips clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
120e58fe957SKim Phillips OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
121e58fe957SKim Phillips printf("PCI clock is 33MHz\n");
122e58fe957SKim Phillips #else
123e58fe957SKim Phillips clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
124e58fe957SKim Phillips printf("PCI clock is 66MHz\n");
125e58fe957SKim Phillips #endif
126e58fe957SKim Phillips udelay(2000);
127e58fe957SKim Phillips
1289993e196SKim Phillips /* Configure PCI Local Access Windows */
1299993e196SKim Phillips pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
130e58fe957SKim Phillips pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
131e58fe957SKim Phillips
1329993e196SKim Phillips pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
133e58fe957SKim Phillips pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
134e58fe957SKim Phillips
135e58fe957SKim Phillips udelay(2000);
136e58fe957SKim Phillips
1379993e196SKim Phillips #ifndef CONFIG_MPC83XX_PCI2
1386aa3d3bfSPeter Tyser mpc83xx_pci_init(1, reg);
1399993e196SKim Phillips #else
1406aa3d3bfSPeter Tyser mpc83xx_pci_init(2, reg);
1419993e196SKim Phillips #endif
142e58fe957SKim Phillips }
143e58fe957SKim Phillips #endif /* CONFIG_PCISLAVE */
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