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Searched refs:VCN (Results 1 – 25 of 29) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_3.c112 vcn_inst = GET_INST(VCN, i); in vcn_v4_0_3_sw_init()
235 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init()
243 VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_hw_init()
354 WREG32_SOC15(VCN, vcn_inst, in vcn_v4_0_3_mc_resume()
770 VCN, 0, regUVD_MPC_CNTL), in vcn_v4_0_3_start_dpg_mode()
1359 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_RPTR); in vcn_v4_0_3_unified_ring_get_rptr()
1379 return RREG32_SOC15(VCN, GET_INST(VCN, ring->me), in vcn_v4_0_3_unified_ring_get_wptr()
1401 WREG32_SOC15(VCN, GET_INST(VCN, ring->me), regUVD_RB_WPTR, in vcn_v4_0_3_unified_ring_set_wptr()
1469 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == in vcn_v4_0_3_is_idle()
1489 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, in vcn_v4_0_3_wait_for_idle()
[all …]
H A Dvcn_v2_5.c864 VCN, 0, mmUVD_MPC_CNTL), in vcn_v2_5_start_dpg_mode()
911 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
1246 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1250 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1258 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1275 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1279 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1289 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1294 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1321 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
[all …]
H A Dvcn_v4_0.c958 VCN, inst_idx, regUVD_MPC_CNTL), in vcn_v4_0_start_dpg_mode()
962 VCN, inst_idx, regUVD_MPC_SET_MUXA0), in vcn_v4_0_start_dpg_mode()
969 VCN, inst_idx, regUVD_MPC_SET_MUXB0), in vcn_v4_0_start_dpg_mode()
976 VCN, inst_idx, regUVD_MPC_SET_MUX), in vcn_v4_0_start_dpg_mode()
997 VCN, inst_idx, regUVD_MASTINT_EN), in vcn_v4_0_start_dpg_mode()
1064 WREG32_SOC15(VCN, i, regUVD_STATUS, tmp); in vcn_v4_0_start()
1115 WREG32_SOC15(VCN, i, regUVD_MPC_SET_MUX, in vcn_v4_0_start()
1185 WREG32_SOC15(VCN, i, regVCN_RB1_DB_CTRL, in vcn_v4_0_start()
1197 WREG32_SOC15(VCN, i, regUVD_RB_RPTR, 0); in vcn_v4_0_start()
1198 WREG32_SOC15(VCN, i, regUVD_RB_WPTR, 0); in vcn_v4_0_start()
[all …]
H A Dvcn_v3_0.c389 RREG32_SOC15(VCN, i, mmUVD_STATUS))) { in vcn_v3_0_hw_fini()
987 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
991 VCN, inst_idx, mmUVD_MPC_SET_MUXA0), in vcn_v3_0_start_dpg_mode()
998 VCN, inst_idx, mmUVD_MPC_SET_MUXB0), in vcn_v3_0_start_dpg_mode()
1005 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1032 VCN, inst_idx, mmUVD_MASTINT_EN), in vcn_v3_0_start_dpg_mode()
1118 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v3_0_start()
1169 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v3_0_start()
1251 WREG32_SOC15(VCN, i, mmUVD_SCRATCH2, 0); in vcn_v3_0_start()
1253 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v3_0_start()
[all …]
H A Dvcn_v2_0.c276 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) in vcn_v2_0_hw_fini()
498 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
505 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
507 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v2_0_disable_clock_gating()
528 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v2_0_disable_clock_gating()
530 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
551 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
665 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
688 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
973 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); in vcn_v2_0_start()
[all …]
H A Dvcn_v1_0.c242 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) { in vcn_v1_0_hw_fini()
465 WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
469 WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
472 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
480 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
482 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE); in vcn_v1_0_disable_clock_gating()
503 WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data); in vcn_v1_0_disable_clock_gating()
505 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
526 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
603 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
[all …]
H A Damdgpu_vcn.h137 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
141 RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_DATA); \
147 WREG32_SOC15(VCN, GET_INST(VCN, inst_idx), \
150 VCN, GET_INST(VCN, inst_idx), \
H A Djpeg_v4_0.c175 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL, in jpeg_v4_0_hw_init()
435 header.total_size = RREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE); in jpeg_v4_0_start_sriov()
476 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); in jpeg_v4_0_start_sriov()
477 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); in jpeg_v4_0_start_sriov()
480 tmp = RREG32_SOC15(VCN, 0, regMMSCH_VF_VMID); in jpeg_v4_0_start_sriov()
484 WREG32_SOC15(VCN, 0, regMMSCH_VF_VMID, tmp); in jpeg_v4_0_start_sriov()
488 WREG32_SOC15(VCN, 0, regMMSCH_VF_CTX_SIZE, size); in jpeg_v4_0_start_sriov()
491 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); in jpeg_v4_0_start_sriov()
497 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_HOST, param); in jpeg_v4_0_start_sriov()
504 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); in jpeg_v4_0_start_sriov()
H A Djpeg_v4_0_3.c245 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_LO, lower_32_bits(ctx_addr)); in jpeg_v4_0_3_start_sriov()
246 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_ADDR_HI, upper_32_bits(ctx_addr)); in jpeg_v4_0_3_start_sriov()
248 tmp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID); in jpeg_v4_0_3_start_sriov()
251 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_VMID, tmp); in jpeg_v4_0_3_start_sriov()
254 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_CTX_SIZE, size); in jpeg_v4_0_3_start_sriov()
256 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); in jpeg_v4_0_3_start_sriov()
259 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_HOST, param); in jpeg_v4_0_3_start_sriov()
267 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); in jpeg_v4_0_3_start_sriov()
333 VCN, GET_INST(VCN, i), in jpeg_v4_0_3_hw_init()
1169 NULL, 0, GET_INST(VCN, jpeg_inst), in jpeg_v4_0_3_inst_query_ras_error_count()
[all …]
/openbmc/linux/fs/ntfs/
H A Drunlist.h29 VCN vcn; /* vcn = Starting virtual cluster number. */
65 extern LCN ntfs_rl_vcn_to_lcn(const runlist_element *rl, const VCN vcn);
70 const VCN vcn);
73 const runlist_element *rl, const VCN first_vcn,
74 const VCN last_vcn);
78 const VCN first_vcn, const VCN last_vcn, VCN *const stop_vcn);
84 const VCN start, const s64 length);
H A Dattrib.h49 extern int ntfs_map_runlist_nolock(ntfs_inode *ni, VCN vcn,
51 extern int ntfs_map_runlist(ntfs_inode *ni, VCN vcn);
53 extern LCN ntfs_attr_vcn_to_lcn_nolock(ntfs_inode *ni, const VCN vcn,
57 const VCN vcn, ntfs_attr_search_ctx *ctx);
61 const VCN lowest_vcn, const u8 *val, const u32 val_len,
H A Dlcnalloc.h30 const VCN start_vcn, const s64 count, const LCN start_lcn,
34 extern s64 __ntfs_cluster_free(ntfs_inode *ni, const VCN start_vcn,
93 static inline s64 ntfs_cluster_free(ntfs_inode *ni, const VCN start_vcn, in ntfs_cluster_free()
H A Drunlist.c527 VCN marker_vcn = 0; in ntfs_runlists_merge()
738 VCN vcn; /* Current vcn. */ in ntfs_mapping_pairs_decompress()
752 attr->data.non_resident.lowest_vcn) < (VCN)0) { in ntfs_mapping_pairs_decompress()
900 VCN max_cluster; in ntfs_mapping_pairs_decompress()
990 LCN ntfs_rl_vcn_to_lcn(const runlist_element *rl, const VCN vcn) in ntfs_rl_vcn_to_lcn()
1039 runlist_element *ntfs_rl_find_vcn_nolock(runlist_element *rl, const VCN vcn) in ntfs_rl_find_vcn_nolock()
1118 const runlist_element *rl, const VCN first_vcn, in ntfs_get_size_for_mapping_pairs()
1119 const VCN last_vcn) in ntfs_get_size_for_mapping_pairs()
1311 const VCN first_vcn, const VCN last_vcn, VCN *const stop_vcn) in ntfs_mapping_pairs_build()
1631 const VCN start, const s64 length) in ntfs_rl_punch_nolock()
[all …]
H A Dtypes.h29 typedef s64 VCN; typedef
H A Daops.c167 VCN vcn; in ntfs_read_block()
242 vcn = (VCN)iblock << blocksize_bits >> in ntfs_read_block()
244 vcn_ofs = ((VCN)iblock << blocksize_bits) & in ntfs_read_block()
533 VCN vcn; in ntfs_write_block()
701 vcn = (VCN)block << blocksize_bits; in ntfs_write_block()
1004 VCN vcn; in ntfs_write_mst_block()
1010 vcn = (VCN)block << bh_size_bits; in ntfs_write_mst_block()
H A Dattrib.c70 int ntfs_map_runlist_nolock(ntfs_inode *ni, VCN vcn, ntfs_attr_search_ctx *ctx) in ntfs_map_runlist_nolock()
72 VCN end_vcn; in ntfs_map_runlist_nolock()
100 VCN allocated_size_vcn; in ntfs_map_runlist_nolock()
284 int ntfs_map_runlist(ntfs_inode *ni, VCN vcn) in ntfs_map_runlist()
327 LCN ntfs_attr_vcn_to_lcn_nolock(ntfs_inode *ni, const VCN vcn, in ntfs_attr_vcn_to_lcn_nolock()
450 runlist_element *ntfs_attr_find_vcn_nolock(ntfs_inode *ni, const VCN vcn, in ntfs_attr_find_vcn_nolock()
869 const IGNORE_CASE_BOOL ic, const VCN lowest_vcn, in ntfs_external_attr_find()
1199 const VCN lowest_vcn, const u8 *val, const u32 val_len, in ntfs_attr_lookup()
1917 VCN vcn; in ntfs_attr_extend_allocation()
H A Dlcnalloc.c132 runlist_element *ntfs_cluster_alloc(ntfs_volume *vol, const VCN start_vcn, in ntfs_cluster_alloc()
835 s64 __ntfs_cluster_free(ntfs_inode *ni, const VCN start_vcn, s64 count, in __ntfs_cluster_free()
916 VCN vcn; in __ntfs_cluster_free()
H A Dcompress.c478 VCN vcn; in ntfs_read_compressed_block()
481 VCN start_vcn = (((s64)index << PAGE_SHIFT) & ~cb_size_mask) >> in ntfs_read_compressed_block()
487 VCN end_vcn = ((((s64)(index + 1UL) << PAGE_SHIFT) + cb_size - 1) in ntfs_read_compressed_block()
H A Dfile.c566 VCN vcn, highest_vcn = 0, cpos, cend, bh_cpos, bh_cend; in ntfs_prepare_pages_for_non_resident_write()
638 VCN cdelta; in ntfs_prepare_pages_for_non_resident_write()
1729 VCN last_vcn; in ntfs_perform_write()
1769 VCN vcn; in ntfs_perform_write()
H A Dindex.c108 VCN vcn, old_vcn; in ntfs_index_lookup()
H A Dmft.c525 VCN vcn; in ntfs_sync_mft_mirror()
531 vcn = ((VCN)mft_no << vol->mft_record_size_bits) + in ntfs_sync_mft_mirror()
718 VCN vcn; in write_mft_record_nolock()
724 vcn = ((VCN)ni->mft_no << vol->mft_record_size_bits) + in write_mft_record_nolock()
1712 VCN old_last_vcn; in ntfs_mft_data_extend_allocation_nolock()
H A Dlogfile.c714 VCN vcn, end_vcn; in ntfs_empty_logfile()
/openbmc/linux/Documentation/gpu/amdgpu/
H A Ddgpu-asic-info-table.csv1 Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version
17 MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2
18 MI200, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0
19 AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
20 AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0…
21 AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
22 AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
23 AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
24 AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
25 AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0
[all …]
H A Dapu-asic-info-table.csv1 Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version, MP0 v…
3 … Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0, 10.0.0
4 Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2, 11.0.3
5 Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.…
6 SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1, 11.5.0
7 …en 7x30 series, GREEN SARDINE / Cezanne / Barcelo / Barcelo-R, DCN 2.1, 9.3, VCN 2.2, 4.1.1, 12.0.1
8 …/ Ryzen 7x36 series, YELLOW CARP / Rembrandt / Rembrandt-R, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3
H A Damdgpu-glossary.rst122 VCN

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