Lines Matching refs:VCN
94 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING); in vcn_v2_5_early_init()
174 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9); in vcn_v2_5_sw_init()
176 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0); in vcn_v2_5_sw_init()
178 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1); in vcn_v2_5_sw_init()
180 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD); in vcn_v2_5_sw_init()
182 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP); in vcn_v2_5_sw_init()
355 RREG32_SOC15(VCN, i, mmUVD_STATUS))) in vcn_v2_5_hw_fini()
425 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
427 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
429 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
432 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
434 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
437 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, in vcn_v2_5_mc_resume()
440 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size); in vcn_v2_5_mc_resume()
443 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
445 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
447 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v2_5_mc_resume()
448 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE); in vcn_v2_5_mc_resume()
451 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
453 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
455 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0); in vcn_v2_5_mc_resume()
456 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE); in vcn_v2_5_mc_resume()
459 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
461 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
463 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0); in vcn_v2_5_mc_resume()
464 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v2_5_mc_resume()
478 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
481 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
484 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
487 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
489 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
491 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
496 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
499 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
503 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_mc_resume_dpg_mode()
509 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
512 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
517 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
520 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
523 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
526 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
528 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
530 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
533 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
537 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
540 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
543 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
545 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
549 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
552 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
555 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
557 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v2_5_mc_resume_dpg_mode()
562 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
581 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
588 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
590 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
612 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
614 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
616 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
637 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
640 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE); in vcn_v2_5_disable_clock_gating()
665 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data); in vcn_v2_5_disable_clock_gating()
667 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
678 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
715 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
719 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
723 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
727 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
746 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
753 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
755 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
775 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
777 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
788 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
805 SOC15_DPG_MODE_OFFSET(VCN, 0, mmVCN_RAS_CNTL), in vcn_v2_6_enable_ras()
810 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_VCPU_INT_EN), in vcn_v2_6_enable_ras()
815 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN), in vcn_v2_6_enable_ras()
826 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1, in vcn_v2_5_start_dpg_mode()
829 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS); in vcn_v2_5_start_dpg_mode()
832 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp); in vcn_v2_5_start_dpg_mode()
845 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
849 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
861 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
864 VCN, 0, mmUVD_MPC_CNTL), in vcn_v2_5_start_dpg_mode()
868 VCN, 0, mmUVD_MPC_SET_MUXA0), in vcn_v2_5_start_dpg_mode()
875 VCN, 0, mmUVD_MPC_SET_MUXB0), in vcn_v2_5_start_dpg_mode()
882 VCN, 0, mmUVD_MPC_SET_MUX), in vcn_v2_5_start_dpg_mode()
890 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect); in vcn_v2_5_start_dpg_mode()
892 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect); in vcn_v2_5_start_dpg_mode()
896 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
902 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect); in vcn_v2_5_start_dpg_mode()
907 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect); in vcn_v2_5_start_dpg_mode()
911 VCN, 0, mmUVD_MASTINT_EN), in vcn_v2_5_start_dpg_mode()
925 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start_dpg_mode()
928 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
934 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0); in vcn_v2_5_start_dpg_mode()
937 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR, in vcn_v2_5_start_dpg_mode()
941 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_5_start_dpg_mode()
943 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_5_start_dpg_mode()
947 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start_dpg_mode()
949 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0); in vcn_v2_5_start_dpg_mode()
951 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start_dpg_mode()
952 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start_dpg_mode()
957 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_start_dpg_mode()
981 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0, in vcn_v2_5_start()
985 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY; in vcn_v2_5_start()
986 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp); in vcn_v2_5_start()
999 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1003 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0, in vcn_v2_5_start()
1007 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL); in vcn_v2_5_start()
1009 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8| in vcn_v2_5_start()
1016 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v2_5_start()
1019 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v2_5_start()
1022 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0, in vcn_v2_5_start()
1029 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0, in vcn_v2_5_start()
1036 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v2_5_start()
1049 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, in vcn_v2_5_start()
1051 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG, in vcn_v2_5_start()
1055 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0, in vcn_v2_5_start()
1059 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0, in vcn_v2_5_start()
1062 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1069 status = RREG32_SOC15(VCN, i, mmUVD_STATUS); in vcn_v2_5_start()
1082 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_start()
1086 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_start()
1099 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), in vcn_v2_5_start()
1104 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0, in vcn_v2_5_start()
1107 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0); in vcn_v2_5_start()
1117 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp); in vcn_v2_5_start()
1121 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW, in vcn_v2_5_start()
1123 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH, in vcn_v2_5_start()
1127 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0); in vcn_v2_5_start()
1129 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR); in vcn_v2_5_start()
1130 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR, in vcn_v2_5_start()
1136 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1137 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1138 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1139 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1140 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_start()
1145 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1146 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_start()
1147 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_start()
1148 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1149 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_start()
1170 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in vcn_v2_5_mmsch_start()
1171 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); in vcn_v2_5_mmsch_start()
1174 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID); in vcn_v2_5_mmsch_start()
1178 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data); in vcn_v2_5_mmsch_start()
1181 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size); in vcn_v2_5_mmsch_start()
1184 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0); in vcn_v2_5_mmsch_start()
1190 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001); in vcn_v2_5_mmsch_start()
1192 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1196 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP); in vcn_v2_5_mmsch_start()
1239 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), in vcn_v2_5_sriov_start()
1246 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1250 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1255 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0); in vcn_v2_5_sriov_start()
1258 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1262 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1267 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), in vcn_v2_5_sriov_start()
1272 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0), in vcn_v2_5_sriov_start()
1275 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1279 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1283 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1), in vcn_v2_5_sriov_start()
1286 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1), in vcn_v2_5_sriov_start()
1289 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1294 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1299 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2), in vcn_v2_5_sriov_start()
1302 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2), in vcn_v2_5_sriov_start()
1309 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), in vcn_v2_5_sriov_start()
1312 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), in vcn_v2_5_sriov_start()
1315 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE), in vcn_v2_5_sriov_start()
1321 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1325 SOC15_REG_OFFSET(VCN, i, in vcn_v2_5_sriov_start()
1337 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp); in vcn_v2_5_sriov_start()
1357 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1361 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR); in vcn_v2_5_stop_dpg_mode()
1362 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1364 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2); in vcn_v2_5_stop_dpg_mode()
1365 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1367 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF; in vcn_v2_5_stop_dpg_mode()
1368 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1370 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1374 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0, in vcn_v2_5_stop_dpg_mode()
1394 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1402 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1407 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2); in vcn_v2_5_stop()
1409 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp); in vcn_v2_5_stop()
1413 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1418 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), in vcn_v2_5_stop()
1423 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), in vcn_v2_5_stop()
1428 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0, in vcn_v2_5_stop()
1432 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0); in vcn_v2_5_stop()
1437 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), in vcn_v2_5_stop()
1459 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE) & in vcn_v2_5_pause_dpg_mode()
1463 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1471 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1474 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v2_5_pause_dpg_mode()
1479 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_pause_dpg_mode()
1487 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1488 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
1489 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
1490 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1491 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1497 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
1498 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
1499 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4); in vcn_v2_5_pause_dpg_mode()
1500 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1501 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_pause_dpg_mode()
1505 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), in vcn_v2_5_pause_dpg_mode()
1508 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v2_5_pause_dpg_mode()
1513 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data); in vcn_v2_5_pause_dpg_mode()
1514 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
1534 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR); in vcn_v2_5_dec_ring_get_rptr()
1551 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR); in vcn_v2_5_dec_ring_get_wptr()
1569 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_dec_ring_set_wptr()
1615 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR); in vcn_v2_5_enc_ring_get_rptr()
1617 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2); in vcn_v2_5_enc_ring_get_rptr()
1635 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR); in vcn_v2_5_enc_ring_get_wptr()
1640 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2); in vcn_v2_5_enc_ring_get_wptr()
1660 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
1667 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in vcn_v2_5_enc_ring_set_wptr()
1737 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1751 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()
1948 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS); in vcn_v2_6_query_poison_by_instance()