242 		 RREG32_SOC15(VCN, 0, mmUVD_STATUS))) {  in vcn_v1_0_hw_fini()
456 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
465 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
467 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
469 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
472 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
480 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
482 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
503 	WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
505 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
526 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
529 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);  in vcn_v1_0_disable_clock_gating()
554 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);  in vcn_v1_0_disable_clock_gating()
556 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);  in vcn_v1_0_disable_clock_gating()
567 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v1_0_disable_clock_gating()
582 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
589 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
591 	data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);  in vcn_v1_0_enable_clock_gating()
593 	WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);  in vcn_v1_0_enable_clock_gating()
596 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
603 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
605 	data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
626 	WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
628 	data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);  in vcn_v1_0_enable_clock_gating()
639 	WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);  in vcn_v1_0_enable_clock_gating()
713 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_disable_static_power_gating()
714 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);  in vcn_1_0_disable_static_power_gating()
727 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_disable_static_power_gating()
728 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF);  in vcn_1_0_disable_static_power_gating()
733 	data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);  in vcn_1_0_disable_static_power_gating()
738 	WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);  in vcn_1_0_disable_static_power_gating()
747 		data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);  in vcn_1_0_enable_static_power_gating()
750 		WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);  in vcn_1_0_enable_static_power_gating()
765 		WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);  in vcn_1_0_enable_static_power_gating()
778 		SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);  in vcn_1_0_enable_static_power_gating()
1343 	return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);  in vcn_v1_0_is_idle()
1351 	ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,  in vcn_v1_0_wait_for_idle()