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Searched refs:UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h785 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x00000007 macro
H A Duvd_4_2_sh_mask.h544 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 macro
H A Duvd_3_1_sh_mask.h540 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 macro
H A Duvd_6_0_sh_mask.h578 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 macro
H A Duvd_5_0_sh_mask.h576 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT 0x7 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2745 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT macro
H A Dvcn_2_0_0_sh_mask.h2741 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT macro
H A Dvcn_2_6_0_sh_mask.h98 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT macro
H A Dvcn_3_0_0_sh_mask.h3803 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT macro
H A Dvcn_4_0_0_sh_mask.h4049 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT macro
H A Dvcn_4_0_3_sh_mask.h4085 #define UVD_VCPU_CNTL__RBBM_SOFT_RESET__SHIFT macro