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Searched refs:UVD_SUVD_CGC_GATE__SRE_MASK (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v6_0.c661 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
694 data1 &= ~(UVD_SUVD_CGC_GATE__SRE_MASK |
1284 data1 |= UVD_SUVD_CGC_GATE__SRE_MASK | in uvd_v6_0_enable_clock_gating()
1409 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
H A Duvd_v5_0.c636 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK | in uvd_v5_0_enable_clock_gating()
749 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
H A Duvd_v7_0.c1622 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1695 suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
H A Dvcn_v4_0_3.c582 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v4_0_3_disable_clock_gating()
H A Dvcn_v2_0.c555 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v2_0_disable_clock_gating()
H A Dvcn_v4_0.c725 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v4_0_disable_clock_gating()
H A Dvcn_v1_0.c530 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v1_0_disable_clock_gating()
H A Dvcn_v2_5.c641 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v2_5_disable_clock_gating()
H A Dvcn_v3_0.c762 data |= (UVD_SUVD_CGC_GATE__SRE_MASK in vcn_v3_0_disable_clock_gating()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h226 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
H A Duvd_6_0_sh_mask.h725 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 macro
H A Duvd_5_0_sh_mask.h723 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x1 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h454 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
H A Dvcn_2_5_sh_mask.h2083 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
H A Dvcn_2_0_0_sh_mask.h3209 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3754 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2819 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
H A Dvcn_4_0_0_sh_mask.h1336 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro
H A Dvcn_4_0_3_sh_mask.h1336 #define UVD_SUVD_CGC_GATE__SRE_MASK … macro