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Searched refs:UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h746 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro
H A Duvd_4_0_sh_mask.h602 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L macro
H A Duvd_4_2_sh_mask.h625 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 macro
H A Duvd_3_1_sh_mask.h619 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 macro
H A Duvd_6_0_sh_mask.h689 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 macro
H A Duvd_5_0_sh_mask.h687 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1273 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro
H A Dvcn_2_5_sh_mask.h2920 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2891 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro
H A Dvcn_2_6_0_sh_mask.h3244 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro
H A Dvcn_3_0_0_sh_mask.h4000 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4250 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4293 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK … macro