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Searched refs:UVD_POWER_STATUS__UVD_PG_EN_MASK (Results 1 – 18 of 18) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h42 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Duvd_6_0_sh_mask.h927 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 macro
H A Duvd_5_0_sh_mask.h939 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x100 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h83 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_2_5_sh_mask.h1523 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_2_0_0_sh_mask.h1520 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2961 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_3_0_0_sh_mask.h2057 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_4_0_0_sh_mask.h6350 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
H A Dvcn_4_0_3_sh_mask.h7154 #define UVD_POWER_STATUS__UVD_PG_EN_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c748 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_0_disable_static_power_gating()
806 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_0_start_dpg_mode()
H A Dvcn_v4_0.c592 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_disable_static_power_gating()
926 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_start_dpg_mode()
H A Dvcn_v1_0.c736 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_1_0_disable_static_power_gating()
977 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v1_0_start_dpg_mode()
H A Dvcn_v3_0.c640 UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v3_0_disable_static_power_gating()
954 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v3_0_start_dpg_mode()
H A Duvd_v6_0.c1483 WREG32(mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK); in uvd_v6_0_set_powergating_state()
H A Dvcn_v4_0_3.c743 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v4_0_3_start_dpg_mode()
H A Duvd_v7_0.c1764 WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
H A Dvcn_v2_5.c831 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK; in vcn_v2_5_start_dpg_mode()