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Searched refs:UVD_MPC_SET_MUXA1__VARA_5_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h612 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
H A Duvd_4_0_sh_mask.h506 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003fL macro
H A Duvd_3_1_sh_mask.h487 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
H A Duvd_4_2_sh_mask.h491 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
H A Duvd_6_0_sh_mask.h525 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
H A Duvd_5_0_sh_mask.h523 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x3f macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1119 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
H A Dvcn_2_5_sh_mask.h2860 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2625 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2852 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3933 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4183 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4226 #define UVD_MPC_SET_MUXA1__VARA_5_MASK … macro