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Searched refs:UVD_MPC_SET_MUXA0__VARA_3_MASK (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h606 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro
H A Duvd_4_0_sh_mask.h502 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00fc0000L macro
H A Duvd_3_1_sh_mask.h483 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 macro
H A Duvd_4_2_sh_mask.h487 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 macro
H A Duvd_6_0_sh_mask.h521 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 macro
H A Duvd_5_0_sh_mask.h519 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0xfc0000 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1113 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro
H A Dvcn_2_5_sh_mask.h2854 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro
H A Dvcn_2_0_0_sh_mask.h2619 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro
H A Dvcn_2_6_0_sh_mask.h2846 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro
H A Dvcn_3_0_0_sh_mask.h3927 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro
H A Dvcn_4_0_0_sh_mask.h4177 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro
H A Dvcn_4_0_3_sh_mask.h4220 #define UVD_MPC_SET_MUXA0__VARA_3_MASK … macro