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Searched refs:UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_0_sh_mask.h209 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x00000004 macro
H A Duvd_4_2_sh_mask.h276 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 macro
H A Duvd_3_1_sh_mask.h276 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 macro
H A Duvd_6_0_sh_mask.h302 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 macro
H A Duvd_5_0_sh_mask.h300 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT 0x4 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_sh_mask.h2030 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT … macro
H A Dvcn_2_0_0_sh_mask.h1982 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT … macro
H A Dvcn_2_6_0_sh_mask.h3701 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT … macro
H A Dvcn_3_0_0_sh_mask.h2760 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT … macro
H A Dvcn_4_0_0_sh_mask.h3878 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT … macro
H A Dvcn_4_0_3_sh_mask.h3913 #define UVD_CGC_UDEC_STATUS__CM_DCLK__SHIFT … macro