| /openbmc/linux/arch/arm/mm/ |
| H A D | proc-v7-3level.S | 50 mcrr p15, 0, rpgdl, rpgdh, c2 @ set TTB 0
120 mov \tmp, #TTB_EAE @ for TTB control egister
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| H A D | proc-v7-2level.S | 58 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
147 mcr p15, 0, \zero, c2, c0, 2 @ TTB control register
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| H A D | proc-v7.S | 142 mrrc p15, 1, r5, r7, c2 @ TTB 1
144 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
146 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
167 mcrr p15, 0, r1, ip, c2 @ TTB 0
168 mcrr p15, 1, r5, r7, c2 @ TTB 1
172 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
173 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
175 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
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| H A D | proc-v6.S | 106 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
168 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
212 mcr p15, 0, r0, c2, c0, 2 @ TTB control register
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| H A D | proc-arm920.S | 393 mcr p15, 0, r1, c2, c0, 0 @ TTB address
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| H A D | proc-arm926.S | 408 mcr p15, 0, r1, c2, c0, 0 @ TTB address
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| H A D | proc-feroceon.S | 528 mcr p15, 0, r1, c2, c0, 0 @ TTB address
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| /openbmc/u-boot/arch/sh/include/asm/ |
| H A D | cpu_sh7750.h | 23 #define TTB 0xFF000008 macro
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| H A D | cpu_sh7723.h | 22 #define TTB 0xFF000008 macro
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| H A D | cpu_sh7724.h | 22 #define TTB 0xFF000008 macro
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| H A D | cpu_sh7720.h | 27 #define TTB 0xFFFFFFF8 macro
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| H A D | cpu_sh7780.h | 21 #define TTB 0xFF000008 macro
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| H A D | cpu_sh7722.h | 22 #define TTB 0xFF000008 macro
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| /openbmc/linux/drivers/iommu/ |
| H A D | omap-iommu-debug.c | 54 pr_reg(TTB); in omap2_iommu_dump_ctx()
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