| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | brcm,bcm2835-spi.txt | 1 Broadcom BCM2835 SPI0 controller
4 SPI0, and the other known as the "Universal SPI Master"; part of the
5 auxiliary block. This binding applies to the SPI0 controller.
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| H A D | brcm,bcm2835-aux-spi.txt | 4 SPI0, and the other known as the "Universal SPI Master"; part of the
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| H A D | spi-orion.txt | 74 <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>, /* SPI0-DEV1 */
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| /openbmc/u-boot/board/renesas/sh7752evb/ |
| H A D | lowlevel_init.S | 29 write16 PDCR_A, PDCR_D ! SPI0
30 write16 PGCR_A, PGCR_D ! SPI0, GETHER MDIO gate(PTG1)
33 write16 PSEL1_A, PSEL1_D ! SPI0
34 write16 PSEL2_A, PSEL2_D ! SPI0
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | armada-8040-clearfog-gt-8k.dts | 211 * [7] CP1 SPI0 CSn1 (FXS)
212 * [8] CP1 SPI0 CSn0 (TPM)
213 * [9.11]CP1 SPI0 MOSI/MISO/CLK
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| H A D | hi3798cv200-poplar.dts | 202 label = "LS-SPI0";
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| H A D | stih410-b2260.dts | 91 label = "LS-SPI0";
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| H A D | zynqmp-zcu100-revC.dts | 283 label = "LS-SPI0";
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| H A D | kirkwood.dtsi | 93 * Default SPI0 pinctrl setting with CSn on mpp0,
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | al,alpine-msix.txt | 13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
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| /openbmc/linux/arch/sh/kernel/cpu/sh4a/ |
| H A D | setup-sh7770.c | 346 SPI0, SPI1, enumerator
381 INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
413 INTC_GROUP(SPI, SPI0, SPI1),
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| H A D | setup-sh7757.c | 800 SPI0, SPI1, enumerator
878 INTC_VECT(SPI0, 0xcc0),
974 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
1071 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
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| /openbmc/linux/arch/arm/boot/dts/intel/socfpga/ |
| H A D | socfpga_cyclone5_chameleon96.dts | 108 label = "LS-SPI0";
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| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-clearfog-gt-8k.dts | 430 * [7] CP1 SPI0 CSn1 (FXS)
431 * [8] CP1 SPI0 CSn0 (TPM)
432 * [9.11]CP1 SPI0 MOSI/MISO/CLK
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3399-rock960.dts | 133 /* On Low speed expansion (LS-SPI0) */
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| /openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hi3798cv200-poplar.dts | 195 label = "LS-SPI0";
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stih410-b2260.dts | 113 label = "LS-SPI0";
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| H A D | stm32mp157a-stinger96.dtsi | 277 /* LS-SPI0 */
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| /openbmc/u-boot/doc/device-tree-bindings/pinctrl/ |
| H A D | marvell,mvebu-pinctrl.txt | 40 * SPI0 [0-3]
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | samsung,exynos7885-clock.yaml | 130 - description: SPI0 clock (from CMU_TOP)
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| /openbmc/u-boot/doc/driver-model/ |
| H A D | pmic-framework.txt | 52 | or SPI0 | |_ REGULATOR device (ldo/... ops) |--> BUCK out 1
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| /openbmc/linux/arch/arm64/boot/dts/allwinner/ |
| H A D | sun50i-h6-pine-h64.dts | 304 * Disable SPI0 in here, to prefer the more useful eMMC. U-Boot can
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| /openbmc/u-boot/board/sunxi/ |
| H A D | README.sunxi64 | 86 3) Initialize the SPI0 controller and try to access a NOR flash connected to
128 can be connected to the SPI0/CS0 pins on the PI-2 headers.
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| /openbmc/linux/arch/arm/boot/dts/marvell/ |
| H A D | kirkwood.dtsi | 94 * Default SPI0 pinctrl setting with CSn on mpp0,
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mq-thor96.dts | 114 /* LS-SPI0 */
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